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  git clone http://v3vee.org/palacios/palacios.web/palacios.git
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  cd palacios
  git checkout --track -b devel origin/devel
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added device checkpoint hooks
[palacios.git] / palacios / src / devices / apic.c
diff --git a/palacios/src/devices/apic.c b/palacios/src/devices/apic.c
index 9bf7438..6b21f81 100644 (file)
--- a/palacios/src/devices/apic.c
+++ b/palacios/src/devices/apic.c
@@ -740,20 +740,7 @@ static int deliver_ipi(struct apic_state * src_apic,
                break;
            }
 
-           // Write the RIP, CS, and descriptor
-           // assume the rest is already good to go
-           //
-           // vector VV -> rip at 0
-           //              CS = VV00
-           //  This means we start executing at linear address VV000
-           //
-           // So the selector needs to be VV00
-           // and the base needs to be VV000
-           //
-           dst_core->rip = 0;
-           dst_core->segments.cs.selector = vector << 8;
-           dst_core->segments.cs.limit = 0xffff;
-           dst_core->segments.cs.base = vector << 12;
+           v3_reset_vm_core(dst_core, vector);
 
            PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
                       vector, dst_core->segments.cs.selector, dst_core->vcpu_id);
@@ -769,10 +756,18 @@ static int deliver_ipi(struct apic_state * src_apic,
            
            break;                                                      
        }
+
+       case APIC_EXTINT_DELIVERY: // EXTINT
+           /* Two possible things to do here: 
+            * 1. Ignore the IPI and assume the 8259a (PIC) will handle it
+            * 2. Add 32 to the vector and inject it...
+            * We probably just want to do 1 here, and assume the raise_irq() will hit the 8259a.
+            */
+           return 0;
+
        case APIC_SMI_DELIVERY: 
        case APIC_RES1_DELIVERY: // reserved                                            
        case APIC_NMI_DELIVERY:
-       case APIC_EXTINT_DELIVERY: // ExtInt
        default:
            PrintError("IPI %d delivery is unsupported\n", del_mode); 
            return -1;
@@ -1220,7 +1215,7 @@ static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, ui
        *val_ptr = *(((uint8_t *)&val) + byte_addr);
 
     } else if ((length == 2) && 
-              ((reg_addr & 0x3) == 0x3)) {
+              ((reg_addr & 0x3) != 0x3)) {
        uint_t byte_addr = reg_addr & 0x3;
        uint16_t * val_ptr = (uint16_t *)dst;
        *val_ptr = *(((uint16_t *)&val) + byte_addr);
@@ -1362,6 +1357,8 @@ static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, u
            apic->tmr_cur_cnt = op_val;
            break;
        case TMR_DIV_CFG_OFFSET:
+           PrintDebug("apic %u: core %u: setting tmr_div_cfg to 0x%x\n",
+                      apic->lapic_id.val, core->vcpu_id, op_val);
            apic->tmr_div_cfg.val = op_val;
            break;
 
@@ -1655,6 +1652,19 @@ static void apic_update_time(struct guest_info * core,
        }
     
        if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
+           static unsigned int nexits = 0;
+           static unsigned int missed_ints = 0;
+
+           nexits++;
+           missed_ints += tmr_ticks / apic->tmr_init_cnt;
+
+           if ((missed_ints > 0) && (nexits >= 5000)) {
+               V3_Print("apic %u: core %u: missed %u timer interrupts total in last %u exits.\n",
+                        apic->lapic_id.val, core->vcpu_id, missed_ints, nexits); 
+               missed_ints = 0;
+               nexits = 0;
+           }
+
            tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
            apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
        }
@@ -1704,9 +1714,109 @@ static int apic_free(struct apic_dev_state * apic_dev) {
     return 0;
 }
 
+#ifdef V3_CONFIG_CHECKPOINT
+static int apic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+    struct apic_dev_state * apic_state = (struct apic_dev_state *)private_data;
+    int i = 0;
+
+    V3_CHKPT_STD_SAVE(ctx, apic_state->num_apics);
+
+    //V3_CHKPT_STD_SAVE(ctx,apic_state->state_lock);
+    for (i = 0; i < apic_state->num_apics; i++) {
+
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].base_addr);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].base_addr_msr);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].lapic_id);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].apic_ver);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ext_apic_ctrl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].local_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_div_cfg);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].lint0_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].lint1_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].perf_ctr_loc_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].therm_loc_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].err_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].err_status);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].spurious_int);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_cmd);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].log_dst);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].dst_fmt);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].arb_prio);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].task_prio);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].proc_prio);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ext_apic_feature);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].spec_eoi);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_cur_cnt);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_init_cnt);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ext_intr_vec_tbl);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].rem_rd_data);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ipi_state);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_req_reg);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_svc_reg);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_en_reg);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].trig_mode_reg);
+       V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].eoi);
+
+    }
+
+    return 0;
+}
+
+static int apic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+    struct apic_dev_state *apic_state = (struct apic_dev_state *)private_data;
+    int i = 0;
+
+    V3_CHKPT_STD_LOAD(ctx,apic_state->num_apics);
+
+    for (i = 0; i < apic_state->num_apics; i++) {
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].base_addr);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].base_addr_msr);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].lapic_id);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].apic_ver);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ext_apic_ctrl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].local_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_div_cfg);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].lint0_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].lint1_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].perf_ctr_loc_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].therm_loc_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].err_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].err_status);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].spurious_int);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_cmd);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].log_dst);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].dst_fmt);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].arb_prio);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].task_prio);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].proc_prio);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ext_apic_feature);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].spec_eoi);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_cur_cnt);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_init_cnt);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ext_intr_vec_tbl);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].rem_rd_data);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ipi_state);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_req_reg);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_svc_reg);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_en_reg);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].trig_mode_reg);
+       V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].eoi);
+    }
+
+
+    return 0;
+}
+
+#endif
 
 static struct v3_device_ops dev_ops = {
     .free = (int (*)(void *))apic_free,
+#ifdef V3_CONFIG_CHECKPOINT
+    .save = apic_save,
+    .load = apic_load
+#endif
 };
 
 
Public Palacios Development Repository for the V3VEE Project