* and the University of New Mexico. You can find out more at
* http://www.v3vee.org
*
- * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
- * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
+ * Copyright (c) 2012, NWU EECS 441 Transactional Memory Team
+ * Copyright (c) 2012, The V3VEE Project <http://www.v3vee.org>
* All rights reserved.
*
* Author: Maciek Swiech <dotpyfe@u.northwestern.edu>
PrintError(_core->vm_info, _core, "TM %10s | " msg , #label, ##__VA_ARGS__); \
} while (0);
+#ifdef V3_CONFIG_DEBUG_TM_FUNC
#define TM_DBG(core, label, msg, ...) \
do { \
typeof (core) _core = (core); \
PrintDebug(_core->vm_info, _core, "TM %10s | " msg , #label, ##__VA_ARGS__); \
} while (0);
+#else
+#define TM_DBG(cor, label, msg, ...)
+#endif
struct mem_op {
addr_t guest_addr;
depends on DEBUG_ON && EXT_CPU_MAPPER_EDF
config TM_FUNC
- bool "Enable Intel RTM Emulation Support"
+ bool "Enable Intel Transactional Memory Emulation"
default n
+ depends on SVM && QUIX86 && EXPERIMENTAL
help
Enable Palacios to emulate Intel's hardware
transactional memory extensions. This is the
Restricted Transactional Memory (RTM) featureset,
- part of Intel's TSX extensions.
+ part of Intel's TSX extensions.
+
+ Ironically, this feature is only implemented for AMD (SVM)
config DEBUG_TM_FUNC
- bool "Enable RTM debugging output"
- depends on TM_FUNC
+ bool "Enable transactional memory emulation debugging output"
+ depends on DEBUG_ON && TM_FUNC
default n
help
Enable Transactional Memory debugging output
* and the University of New Mexico. You can find out more at
* http://www.v3vee.org
*
- * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
- * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
+ * Copyright (c) 2012, NWU EECS 441 Transactional Memory Team
+ * Copyright (c) 2012, The V3VEE Project <http://www.v3vee.org>
* All rights reserved.
*
* Author: Maciek Swiech <dotpyfe@u.northwestern.edu>