case MOV_MEM2:
case MOV_2MEM:
case MOV_MEM2AX:
- case MOV_AX2MEM:
- case MOV_IMM2:
+ case MOV_AX2MEM:
case MOVS:
case MOVSX:
case MOVZX:
case OR_IMM2SX_8:
case SUB_IMM2SX_8:
case XOR_IMM2SX_8:
+ case MOV_IMM2:
switch (v3_get_vm_cpu_mode(info)) {
case REAL:
return (instr->prefixes.op_size) ? 4 : 2;
if (instr->prefixes.rex_op_size) {
return 8;
} else {
- return 4;
+ return (instr->prefixes.op_size) ? 2 : 4;
}
case PROTECTED:
case PROTECTED_PAE:
PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
return -1;
}
-
case INVLPG:
switch (v3_get_vm_cpu_mode(info)) {
case REAL:
}
- /*
- Segments should be ignored
- // get appropriate segment
- if (instr->prefixes.cs_override) {
- seg = &(core->segments.cs);
- } else if (instr->prefixes.es_override) {
- seg = &(core->segments.es);
- } else if (instr->prefixes.ss_override) {
- seg = &(core->segments.ss);
- } else if (instr->prefixes.fs_override) {
- seg = &(core->segments.fs);
- } else if (instr->prefixes.gs_override) {
- seg = &(core->segments.gs);
- } else {
- seg = &(core->segments.ds);
- }
- */
+
+ //Segments should be ignored
+ // get appropriate segment
+
+ if (instr->prefixes.cs_override) {
+ seg = &(core->segments.cs);
+ } else if (instr->prefixes.es_override) {
+ seg = &(core->segments.es);
+ } else if (instr->prefixes.ss_override) {
+ seg = &(core->segments.ss);
+ } else if (instr->prefixes.fs_override) {
+ seg = &(core->segments.fs);
+ } else if (instr->prefixes.gs_override) {
+ seg = &(core->segments.gs);
+ } else {
+ seg = &(core->segments.ds);
+ }
+
operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
get_addr_width(core, instr));
case REAL:
return decode_rm_operand16(core, instr_ptr, instr, operand, reg_code);
case LONG:
- if (instr->prefixes.rex_op_size) {
+ if (instr->prefixes.rex) {
return decode_rm_operand64(core, instr_ptr, instr, operand, reg_code);
}
case PROTECTED:
instr->instr_length += length;
#ifdef V3_CONFIG_DEBUG_DECODER
+ V3_Print("Decoding Instr at %p\n", (void *)core->rip);
v3_print_instr(instr);
+ V3_Print("CS DB FLag=%x\n", core->segments.cs.db);
#endif
return 0;
case AND_IMM2:
case OR_IMM2:
case SUB_IMM2:
- case XOR_IMM2:
- case MOV_IMM2:{
+ case XOR_IMM2:
+ case MOV_IMM2: {
uint8_t reg_code = 0;
ret = decode_rm_operand(core, instr_ptr, form, instr, &(instr->dst_operand), ®_code);
instr->src_operand.operand = *(uint16_t *)instr_ptr;
} else if (operand_width == 4) {
instr->src_operand.operand = *(uint32_t *)instr_ptr;
+ } else if (operand_width == 8) {
+ instr->src_operand.operand = *(sint32_t *)instr_ptr; // This is a special case for sign extended 64bit ops
} else {
PrintError("Illegal operand width (%d)\n", operand_width);
return -1;
instr->is_str_op = 1;
if (instr->prefixes.rep == 1) {
- instr->str_op_length = MASK(core->vm_regs.rcx, operand_width);
+ instr->str_op_length = MASK(core->vm_regs.rcx, addr_width);
} else {
instr->str_op_length = 1;
}
instr->is_str_op = 1;
if (instr->prefixes.rep == 1) {
- instr->str_op_length = MASK(core->vm_regs.rcx, operand_width);
+ instr->str_op_length = MASK(core->vm_regs.rcx, addr_width);
} else {
instr->str_op_length = 1;
}