uint8_t data_buf[DATA_BUFFER_SIZE];
+
+ uint32_t num_cylinders;
+ uint32_t num_heads;
+ uint32_t num_sectors;
+
void * private_data;
union {
/* IO Operations */
static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
struct ide_drive * drive = get_selected_drive(channel);
+ // This is at top level scope to do the EOT test at the end
struct ide_dma_prd prd_entry;
- uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
- int ret;
- PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
+ // Read in the data buffer....
+ // Read a sector/block at a time until the prd entry is full.
- ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
+ if (drive->drive_type == IDE_DISK) {
+ uint_t bytes_left = drive->transfer_length;
- if (ret != sizeof(struct ide_dma_prd)) {
- PrintError("Could not read PRD\n");
- return -1;
- }
+ // Loop through the disk data
+ while (bytes_left > 0) {
- PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
+ uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
+ uint_t prd_bytes_left = 0;
+ uint_t prd_offset = 0;
+ int ret;
+
+ PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
+
+ ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
+
+ if (ret != sizeof(struct ide_dma_prd)) {
+ PrintError("Could not read PRD\n");
+ return -1;
+ }
+
+ PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
+
+ // loop through the PRD data....
+
+ prd_bytes_left = prd_entry.size;
- ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf);
- if (ret != prd_entry.size) {
- PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
- return -1;
- }
+ while (prd_bytes_left > 0) {
+ uint_t bytes_to_write = (prd_bytes_left > IDE_SECTOR_SIZE) ? IDE_SECTOR_SIZE : prd_bytes_left;
+ if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
+ PrintError("Failed to read next disk sector\n");
+ return -1;
+ }
+
+ drive->current_lba++;
+
+ ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr + prd_offset, bytes_to_write, drive->data_buf);
+
+ if (ret != bytes_to_write) {
+ PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
+ return -1;
+ }
+
+ drive->transfer_index += ret;
+ prd_bytes_left -= ret;
+ prd_offset += ret;
+ bytes_left -= ret;
+ }
+
+ channel->dma_tbl_index++;
+
+ if (drive->transfer_index % IDE_SECTOR_SIZE) {
+ PrintError("We currently don't handle sectors that span PRD descriptors\n");
+ return -1;
+ }
+
+ if ((prd_entry.end_of_table == 1) && (bytes_left > 0)) {
+ PrintError("DMA table not large enough for data transfer...\n");
+ return -1;
+ }
+
+ }
+
+ } else if (drive->drive_type == IDE_CDROM) {
+ PrintError("CDROM DMA not supported\n");
+ return -1;
+ }
/*
drive->irq_flags.io_dir = 1;
*/
+ // Update to the next PRD entry
+
// set DMA status
if (prd_entry.end_of_table) {
- channel->dma_status.active = 0;
- channel->dma_status.err = 0;
- channel->dma_status.int_gen = 1;
-
channel->status.busy = 0;
channel->status.ready = 1;
channel->status.data_req = 0;
channel->status.error = 0;
channel->status.seek_complete = 1;
+
+ channel->dma_status.active = 0;
+ channel->dma_status.err = 0;
}
ide_raise_irq(dev, channel);
uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
struct ide_channel * channel = &(ide->channels[channel_flag]);
+ PrintDebug("IDE: Writing DMA Port %x (%s) (val=%x) (len=%d) (channel=%d)\n",
+ port, dma_port_to_str(port_offset), *(uint32_t *)src, length, channel_flag);
+
switch (port_offset) {
case DMA_CMD_PORT:
channel->dma_cmd.val = *(uint8_t *)src;
break;
- case DMA_STATUS_PORT:
+ case DMA_STATUS_PORT: {
+ uint8_t val = *(uint8_t *)src;
+
if (length != 1) {
PrintError("Invalid read length for DMA status port\n");
return -1;
}
- channel->dma_status.val = *(uint8_t *)src;
+ // weirdness
+ channel->dma_status.val = ((val & 0x60) |
+ (channel->dma_status.val & 0x01) |
+ (channel->dma_status.val & ~val & 0x06));
+
break;
-
+ }
case DMA_PRD_PORT0:
case DMA_PRD_PORT1:
case DMA_PRD_PORT2:
uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
struct ide_channel * channel = &(ide->channels[channel_flag]);
+ PrintDebug("Reading DMA port %d (%x) (channel=%d)\n", port, port, channel_flag);
+
switch (port_offset) {
case DMA_CMD_PORT:
*(uint8_t *)dst = channel->dma_cmd.val;
return -1;
}
- PrintDebug("\tval=%x\n", *(uint32_t *)dst);
+ PrintDebug("\tval=%x (len=%d)\n", *(uint32_t *)dst, length);
return length;
}
break;
case 0xc8: // Read DMA with retry
- case 0xc9: // Read DMA
+ case 0xc9: { // Read DMA
+ uint32_t sect_cnt = (drive->sector_count == 0) ? 256 : drive->sector_count;
+
+ if (ata_get_lba(dev, channel, &(drive->current_lba)) == -1) {
+ ide_abort_command(dev, channel);
+ return 0;
+ }
+
drive->hd_state.cur_sector_num = 1;
+
+ drive->transfer_length = sect_cnt * IDE_SECTOR_SIZE;
+ drive->transfer_index = 0;
+ if (channel->dma_status.active == 1) {
+ // DMA Read
+ if (dma_read(dev, channel) == -1) {
+ PrintError("Failed DMA Read\n");
+ return -1;
+ }
+ }
break;
+ }
case 0xef: // Set Features
// Prior to this the features register has been written to.
// This command tells the drive to check if the new value is supported (the value is drive specific)
drive->transfer_length = 0;
memset(drive->data_buf, 0, sizeof(drive->data_buf));
+ drive->num_cylinders = 0;
+ drive->num_heads = 0;
+ drive->num_sectors = 0;
+
drive->private_data = NULL;
drive->cd_ops = NULL;
pci_dev->config_header.vendor_id = 0x8086;
pci_dev->config_header.device_id = 0x7010;
- pci_dev->config_header.revision = 0x8000;
+ pci_dev->config_header.revision = 0x00;
+ pci_dev->config_header.prog_if = 0x80;
pci_dev->config_header.subclass = 0x01;
pci_dev->config_header.class = 0x01;
pci_dev->config_header.command = 0;
pci_dev->config_header.status = 0x0280;
+
+ ide->ide_pci = pci_dev;
+
+
}
return 0;
+int v3_ide_get_geometry(struct vm_device * ide_dev, int channel_num, int drive_num,
+ uint32_t * cylinders, uint32_t * heads, uint32_t * sectors) {
+
+ struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
+ struct ide_channel * channel = &(ide->channels[channel_num]);
+ struct ide_drive * drive = &(channel->drives[drive_num]);
+
+ if (drive->drive_type == IDE_NONE) {
+ return -1;
+ }
+
+ *cylinders = drive->num_cylinders;
+ *heads = drive->num_heads;
+ *sectors = drive->num_sectors;
+
+ return 0;
+}
+
+
int v3_ide_register_cdrom(struct vm_device * ide_dev,
drive->cd_ops = ops;
+ if (ide->ide_pci) {
+ // Hardcode this for now, but its not a good idea....
+ ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
+ }
+
drive->private_data = private_data;
return 0;
drive->hd_ops = ops;
+ /* this is something of a hack... */
+ drive->num_sectors = 63;
+ drive->num_heads = 16;
+ drive->num_cylinders = (ops->get_capacity(private_data) / 512) / (drive->num_sectors * drive->num_heads);
+
+ if (ide->ide_pci) {
+ // Hardcode this for now, but its not a good idea....
+ ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
+ }
+
+
+
drive->private_data = private_data;
return 0;
#include <palacios/vmm_types.h>
+#include <devices/ide.h>
+
#ifndef DEBUG_NVRAM
#undef PrintDebug
#define PrintDebug(fmt, args...)
#define NVRAM_REG_SHUTDOWN_STATUS 0x0f
#define NVRAM_IBM_HD_DATA 0x12
+#define NVRAM_IDE_TRANSLATION 0x39
#define NVRAM_REG_FLOPPY_TYPE 0x10
#define NVRAM_REG_EQUIPMENT_BYTE 0x14
nvram_state_t dev_state;
uchar_t thereg;
uchar_t mem_state[NVRAM_REG_MAX];
+ uchar_t reg_map[NVRAM_REG_MAX / 8];
+
+ struct vm_device * ide;
uint_t us; //microseconds - for clock update - zeroed every second
uint_t pus; //microseconds - for periodic interrupt - cleared every period
+static void set_reg_num(struct nvram_internal * nvram, uint8_t reg_num) {
+ int major = (reg_num / 8);
+ int minor = reg_num % 8;
+
+ nvram->reg_map[major] |= (0x1 << minor);
+}
+
+static int is_reg_set(struct nvram_internal * nvram, uint8_t reg_num) {
+ int major = (reg_num / 8);
+ int minor = reg_num % 8;
+
+ return (nvram->reg_map[major] & (0x1 << minor)) ? 1 : 0;
+}
+
+
+static void set_memory(struct nvram_internal * nvram, uint8_t reg, uint8_t val) {
+ set_reg_num(nvram, reg);
+ nvram->mem_state[reg] = val;
+}
+
+static int get_memory(struct nvram_internal * nvram, uint8_t reg, uint8_t * val) {
+
+ if (!is_reg_set(nvram, reg)) {
+ *val = 0;
+ return -1;
+ }
+
+ *val = nvram->mem_state[reg];
+ return 0;
+}
+
+
static uchar_t add_to(uchar_t * left, uchar_t * right, uchar_t bcd) {
uchar_t temp;
// 3. Big Mem: 0-4G in 64K
if (bytes > 640 * 1024) {
- nvram->mem_state[NVRAM_REG_BASE_MEMORY_HIGH] = 0x02;
- nvram->mem_state[NVRAM_REG_BASE_MEMORY_LOW] = 0x80;
+ set_memory(nvram, NVRAM_REG_BASE_MEMORY_HIGH, 0x02);
+ set_memory(nvram, NVRAM_REG_BASE_MEMORY_LOW, 0x80);
+
+ // nvram->mem_state[NVRAM_REG_BASE_MEMORY_HIGH] = 0x02;
+ // nvram->mem_state[NVRAM_REG_BASE_MEMORY_LOW] = 0x80;
} else {
uint16_t memk = bytes * 1024;
- nvram->mem_state[NVRAM_REG_BASE_MEMORY_HIGH] = (memk >> 8) & 0x00ff;
- nvram->mem_state[NVRAM_REG_BASE_MEMORY_LOW] = memk & 0x00ff;
+ set_memory(nvram, NVRAM_REG_BASE_MEMORY_HIGH, (memk >> 8) & 0x00ff);
+ set_memory(nvram, NVRAM_REG_BASE_MEMORY_LOW, memk & 0x00ff);
return;
}
if (bytes > (16 * 1024 * 1024)) {
// Set extended memory to 15 MB
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_HIGH] = 0x3C;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_LOW] = 0x00;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_2ND_HIGH]= 0x3C;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_2ND_LOW]= 0x00;
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_HIGH, 0x3C);
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_LOW, 0x00);
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_2ND_HIGH, 0x3C);
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_2ND_LOW, 0x00);
} else {
uint16_t memk = bytes * 1024;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_HIGH] = (memk >> 8) & 0x00ff;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_LOW] = memk & 0x00ff;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_2ND_HIGH]= (memk >> 8) & 0x00ff;
- nvram->mem_state[NVRAM_REG_EXT_MEMORY_2ND_LOW]= memk & 0x00ff;
+
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_HIGH, (memk >> 8) & 0x00ff);
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_LOW, memk & 0x00ff);
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_2ND_HIGH, (memk >> 8) & 0x00ff);
+ set_memory(nvram, NVRAM_REG_EXT_MEMORY_2ND_LOW, memk & 0x00ff);
return;
}
{
// Set the extended memory beyond 16 MB in 64k chunks
uint16_t mem_chunks = (bytes - (1024 * 1024 * 16)) / (1024 * 64);
- nvram->mem_state[NVRAM_REG_AMI_BIG_MEMORY_HIGH] = (mem_chunks >> 8) & 0x00ff;
- nvram->mem_state[NVRAM_REG_AMI_BIG_MEMORY_LOW] = mem_chunks & 0x00ff;
+
+ set_memory(nvram, NVRAM_REG_AMI_BIG_MEMORY_HIGH, (mem_chunks >> 8) & 0x00ff);
+ set_memory(nvram, NVRAM_REG_AMI_BIG_MEMORY_LOW, mem_chunks & 0x00ff);
}
return;
}
+
+
+static void init_harddrives(struct nvram_internal * nvram) {
+ uint8_t hd_data = 0;
+ uint32_t cyls;
+ uint32_t sects;
+ uint32_t heads;
+ int i = 0;
+ int info_base_reg = 0x1b;
+ int type_reg = 0x19;
+
+ // 0x19 == first drive type
+ // 0x1a == second drive type
+
+ // 0x1b == first drive geometry base
+ // 0x24 == second drive geometry base
+
+ // It looks like the BIOS only tracks the disks on the first channel at 0x12?
+ for (i = 0; i < 2; i++) {
+ if (v3_ide_get_geometry(nvram->ide, 0, i, &cyls, &heads, §s) == 0) {
+
+ int info_reg = info_base_reg + (i * 9);
+
+ set_memory(nvram, type_reg + i, 0x2f);
+
+ set_memory(nvram, info_reg, cyls & 0xff);
+ set_memory(nvram, info_reg + 1, (cyls >> 8) & 0xff);
+ set_memory(nvram, info_reg + 2, heads & 0xff);
+
+ // Write precomp cylinder (1 and 2)
+ set_memory(nvram, info_reg + 3, 0xff);
+ set_memory(nvram, info_reg + 4, 0xff);
+
+ // harddrive control byte
+ set_memory(nvram, info_reg + 5, 0xc0 | ((heads > 8) << 3));
+
+ set_memory(nvram, info_reg + 6, cyls & 0xff);
+ set_memory(nvram, info_reg + 7, (cyls >> 8) & 0xff);
+
+ set_memory(nvram, info_reg + 8, sects & 0xff);
+
+ hd_data |= (0xf0 >> (i * 4));
+ }
+ }
+
+ set_memory(nvram, NVRAM_IBM_HD_DATA, hd_data);
+
+ {
+#define TRANSLATE_NONE 0x0
+#define TRANSLATE_LBA 0x1
+#define TRANSLATE_LARGE 0x2
+#define TRANSLATE_RECHS 0x3
+ // We're going to do LBA translation for everything...
+ uint8_t trans = 0;
+
+ for (i = 0; i < 4; i++) {
+ int chan_num = i / 2;
+ int drive_num = i % 2;
+ uint32_t tmp[3];
+
+ if (v3_ide_get_geometry(nvram->ide, chan_num, drive_num, &tmp[0], &tmp[1], &tmp[2]) == 0) {
+ trans |= TRANSLATE_LBA << (i * 2);
+ }
+ }
+
+ set_memory(nvram, NVRAM_IDE_TRANSLATION, trans);
+ }
+}
+
static int init_nvram_state(struct vm_device * dev) {
struct guest_info * info = dev->vm;
- struct nvram_internal * nvram_state = (struct nvram_internal *)dev->private_data;
+ struct nvram_internal * nvram = (struct nvram_internal *)dev->private_data;
- memset(nvram_state->mem_state, 0, NVRAM_REG_MAX);
+ memset(nvram->mem_state, 0, NVRAM_REG_MAX);
+ memset(nvram->reg_map, 0, NVRAM_REG_MAX / 8);
//
// 2 1.44 MB floppy drives
//
#if 1
- nvram_state->mem_state[NVRAM_REG_FLOPPY_TYPE] = 0x44;
+ set_memory(nvram, NVRAM_REG_FLOPPY_TYPE, 0x44);
#else
- nvram_state->mem_state[NVRAM_REG_FLOPPY_TYPE] = 0x00;
+ set_memory(nvram, NVRAM_REG_FLOPPY_TYPE, 0x00);
#endif
//
// For old boot sequence style, do floppy first
//
- nvram_state->mem_state[NVRAM_REG_BOOTSEQ_OLD] = 0x10;
+ set_memory(nvram, NVRAM_REG_BOOTSEQ_OLD, 0x10);
#if 0
// For new boot sequence style, do floppy, cd, then hd
- nvram_state->mem_state[NVRAM_REG_BOOTSEQ_NEW_FIRST] = 0x31;
- nvram_state->mem_state[NVRAM_REG_BOOTSEQ_NEW_SECOND] = 0x20;
+ set_memory(nvram, NVRAM_REG_BOOTSEQ_NEW_FIRST, 0x31);
+ set_memory(nvram, NVRAM_REG_BOOTSEQ_NEW_SECOND, 0x20);
#endif
// For new boot sequence style, do cd, hd, floppy
- nvram_state->mem_state[NVRAM_REG_BOOTSEQ_NEW_FIRST] = 0x23;
- nvram_state->mem_state[NVRAM_REG_BOOTSEQ_NEW_SECOND] = 0x10;
+ set_memory(nvram, NVRAM_REG_BOOTSEQ_NEW_FIRST, 0x23);
+ set_memory(nvram, NVRAM_REG_BOOTSEQ_NEW_SECOND, 0x10);
// Set equipment byte to note 2 floppies, vga display, keyboard,math,floppy
- nvram_state->mem_state[NVRAM_REG_EQUIPMENT_BYTE] = 0x4f;
- // nvram_state->mem_state[NVRAM_REG_EQUIPMENT_BYTE] = 0xf;
+ set_memory(nvram, NVRAM_REG_EQUIPMENT_BYTE, 0x4f);
+ // set_memory(nvram, NVRAM_REG_EQUIPMENT_BYTE, 0xf);
- // This is the harddisk type.... Set accordingly...
- nvram_state->mem_state[NVRAM_IBM_HD_DATA] = 0x20;
-
// Set the shutdown status gently
// soft reset
- nvram_state->mem_state[NVRAM_REG_SHUTDOWN_STATUS] = 0x0;
+ set_memory(nvram, NVRAM_REG_SHUTDOWN_STATUS, 0x0);
// RTC status A
// 00100110 = no update in progress, base=32768 Hz, rate = 1024 Hz
- nvram_state->mem_state[NVRAM_REG_STAT_A] = 0x26;
+ set_memory(nvram, NVRAM_REG_STAT_A, 0x26);
// RTC status B
// 00000100 = not setting, no interrupts, blocked rect signal, bcd mode, 24 hour, normal time
- nvram_state->mem_state[NVRAM_REG_STAT_B] = 0x06;
+ set_memory(nvram, NVRAM_REG_STAT_B, 0x06);
// RTC status C
// No IRQ requested, result not do to any source
- nvram_state->mem_state[NVRAM_REG_STAT_C] = 0x00;
+ set_memory(nvram, NVRAM_REG_STAT_C, 0x00);
// RTC status D
// Battery is OK
- nvram_state->mem_state[NVRAM_REG_STAT_D] = 0x80;
+ set_memory(nvram, NVRAM_REG_STAT_D, 0x80);
// january 1, 2008, 00:00:00
- nvram_state->mem_state[NVRAM_REG_MONTH] = 0x1;
- nvram_state->mem_state[NVRAM_REG_MONTH_DAY] = 0x1;
- nvram_state->mem_state[NVRAM_REG_WEEK_DAY] = 0x1;
- nvram_state->mem_state[NVRAM_REG_YEAR] = 0x08;
-
- nvram_state->us = 0;
- nvram_state->pus = 0;
-
- set_memory_size(nvram_state, info->mem_size);
+ set_memory(nvram, NVRAM_REG_SEC, 0x00);
+ set_memory(nvram, NVRAM_REG_SEC_ALARM, 0x00);
+ set_memory(nvram, NVRAM_REG_MIN, 0x00);
+ set_memory(nvram, NVRAM_REG_MIN_ALARM, 0x00);
+ set_memory(nvram, NVRAM_REG_HOUR, 0x00);
+ set_memory(nvram, NVRAM_REG_HOUR_ALARM, 0x00);
+
+ set_memory(nvram, NVRAM_REG_MONTH, 0x01);
+ set_memory(nvram, NVRAM_REG_MONTH_DAY, 0x1);
+ set_memory(nvram, NVRAM_REG_WEEK_DAY, 0x1);
+ set_memory(nvram, NVRAM_REG_YEAR, 0x08);
+
+ set_memory(nvram, NVRAM_REG_DIAGNOSTIC_STATUS, 0x00);
+
+ nvram->us = 0;
+ nvram->pus = 0;
- nvram_state->dev_state = NVRAM_READY;
- nvram_state->thereg = 0;
+ set_memory_size(nvram, info->mem_size);
+ init_harddrives(nvram);
+
+ nvram->dev_state = NVRAM_READY;
+ nvram->thereg = 0;
return 0;
}
void * src,
uint_t length,
struct vm_device * dev) {
- struct nvram_internal * data = (struct nvram_internal *)dev->private_data;
+ struct nvram_internal * data = (struct nvram_internal *)dev->private_data;
+
memcpy(&(data->thereg), src, 1);
PrintDebug("Writing To NVRAM reg: 0x%x\n", data->thereg);
-
return 1;
}
void * dst,
uint_t length,
struct vm_device * dev) {
+
struct nvram_internal * data = (struct nvram_internal *)dev->private_data;
- memcpy(dst, &(data->mem_state[data->thereg]), 1);
+ if (get_memory(data, data->thereg, (uint8_t *)dst) == -1) {
+ PrintError("Register %d (0x%x) Not set\n", data->thereg, data->thereg);
+ return -1;
+ }
- PrintDebug("nvram_read_data_port(0x%x)=0x%x\n", data->thereg, data->mem_state[data->thereg]);
+ PrintDebug("nvram_read_data_port(0x%x) = 0x%x\n", data->thereg, *(uint8_t *)dst);
// hack
if (data->thereg == NVRAM_REG_STAT_A) {
data->mem_state[data->thereg] ^= 0x80; // toggle Update in progess
}
-
return 1;
}
+
static int nvram_write_data_port(ushort_t port,
void * src,
uint_t length,
struct vm_device * dev) {
+
struct nvram_internal * data = (struct nvram_internal *)dev->private_data;
- memcpy(&(data->mem_state[data->thereg]), src, 1);
+ set_memory(data, data->thereg, *(uint8_t *)src);
- PrintDebug("nvram_write_data_port(0x%x)=0x%x\n", data->thereg, data->mem_state[data->thereg]);
+ PrintDebug("nvram_write_data_port(0x%x) = 0x%x\n",
+ data->thereg, data->mem_state[data->thereg]);
return 1;
}
-struct vm_device * v3_create_nvram() {
+struct vm_device * v3_create_nvram(struct vm_device * ide) {
struct nvram_internal * nvram_state = NULL;
nvram_state = (struct nvram_internal *)V3_Malloc(sizeof(struct nvram_internal) + 1000);
PrintDebug("nvram: internal at %p\n", (void *)nvram_state);
+ nvram_state->ide = ide;
+
struct vm_device * device = v3_create_device("NVRAM", &dev_ops, nvram_state);
return device;
