correct XTEST behavior in RTM code

diff --git a/palacios/include/extensions/trans_mem.h b/palacios/include/extensions/trans_mem.h
index 116cb51..f3c1654 100644 (file)
--- a/palacios/include/extensions/trans_mem.h
+++ b/palacios/include/extensions/trans_mem.h
@@ -27,7 +27,6 @@ From Intel Architecture Instruction Set Extensions Programming Reference, Sectio
 link: http://software.intel.com/sites/default/files/m/9/2/3/41604
 
 - architectural registers need to be saved / restored 
-- exceptions that misuse of TSX instructions can raise
 - abort on interrupts, asynchronous events
 - abort on CPUID, PAUSE
 - abort on non-writeback memory ops, including ifetches to uncacheable mem

diff --git a/palacios/src/extensions/ext_trans_mem.c b/palacios/src/extensions/ext_trans_mem.c
index bffb4d7..8930e5d 100644 (file)
--- a/palacios/src/extensions/ext_trans_mem.c
+++ b/palacios/src/extensions/ext_trans_mem.c
@@ -1894,7 +1894,7 @@ tm_handle_xbegin (struct guest_info * core,
 
     if (tm->TM_MODE == TM_ON) {
         /* TODO: this is actually an indication of nesting, we'll fix this later */
-        TM_ERR(core,UD,"We got here while already in a transactional region!");
+        TM_ERR(core,UD,"We don't support nested transactions yet!\n");
         v3_raise_exception(core, UD_EXCEPTION);
         return -1;
     }
@@ -1947,13 +1947,21 @@ static int
 tm_handle_xtest (struct guest_info * core,
                  struct v3_trans_mem * tm)
 {
+    struct rflags * rf = (struct rflags*)&(core->ctrl_regs.rflags);
+
     // if we are in tm mode, set zf to 0, otherwise 1
     if (tm->TM_MODE == TM_ON) {
-        core->ctrl_regs.rflags &= ~(1ULL << 6);
+        rf->zf = 0;
     } else {
-        core->ctrl_regs.rflags |= (1ULL << 6);
+        rf->zf = 1;
     }
 
+    rf->cf = 0;
+    rf->of = 0;
+    rf->sf = 0;
+    rf->pf = 0;
+    rf->af = 0;
+
     core->rip += XTEST_INSTR_LEN;
 
     return 0;