bar->type = PT_BAR_IO;
} else if (flags & IORESOURCE_MEM) {
if (flags & IORESOURCE_MEM_64) {
- printk("ERROR: 64 Bit BARS not yet supported\n");
- bar->type = PT_BAR_NONE;
+ struct v3_host_pci_bar * hi_bar = &(v3_dev->bars[i + 1]);
+
+ bar->type = PT_BAR_MEM64_LO;
+
+ hi_bar->type = PT_BAR_MEM64_HI;
+ hi_bar->size = bar->size;
+ hi_bar->addr = bar->addr;
+ hi_bar->cacheable = ((flags & IORESOURCE_CACHEABLE) != 0);
+ hi_bar->prefetchable = ((flags & IORESOURCE_PREFETCH) != 0);
+
+ i++;
} else if (flags & IORESOURCE_DMA) {
bar->type = PT_BAR_MEM24;
} else {
hbar->addr, hbar->addr + hbar->size - 1,
hbar->addr);
} else if (hbar->type == PT_BAR_MEM64_LO) {
- PrintError("Don't currently handle 64 bit bars...\n");
+ struct v3_host_pci_bar * hi_hbar = &(state->host_dev->bars[bar_num + 1]);
+ bar_val = PCI_MEM64_LO_BAR_VAL(hi_hbar->addr, hbar->prefetchable);
} else if (hbar->type == PT_BAR_MEM64_HI) {
- PrintError("Don't currently handle 64 bit bars...\n");
+ bar_val = PCI_MEM64_HI_BAR_VAL(hbar->addr, hbar->prefetchable);
+
+ v3_add_shadow_mem(dev->vm, V3_MEM_CORE_ANY,
+ hbar->addr, hbar->addr + hbar->size - 1,
+ hbar->addr);
}