check_vmcs_read(VMCS_CR0_READ_SHDW, &(info->shdw_pg_state.guest_cr0));
check_vmcs_read(VMCS_GUEST_CR3, &(info->ctrl_regs.cr3));
check_vmcs_read(VMCS_GUEST_CR4, &(info->ctrl_regs.cr4));
- check_vmcs_read(VMCS_CR4_READ_SHDW, &(vmx_info->guest_cr4));
+ check_vmcs_read(VMCS_CR4_READ_SHDW, &(info->shdw_pg_state.guest_cr4));
check_vmcs_read(VMCS_GUEST_DR7, &(info->dbg_regs.dr7));
check_vmcs_read(VMCS_GUEST_RFLAGS, &(info->ctrl_regs.rflags));
// Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
- vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
+ vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE );
- core->ctrl_regs.cr3 = core->direct_map_pt;
+ v3_activate_passthrough_pt(core);
// vmx_state->pinbased_ctrls |= NMI_EXIT;
/* Add CR exits */
vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
-
+
+ // Note that we intercept cr4.pae writes
+ // and we have cr4 read-shadowed to the shadow pager's cr4
+
vmx_state->pri_proc_ctrls.invlpg_exit = 1;
/* Add page fault exits */
core->vm_regs.rsp = 0x80000;
((struct rflags *)&(core->ctrl_regs.rflags))->rsvd1 = 1;
-#define GUEST_CR0 0x80010031
-#define GUEST_CR4 0x00002010
- core->ctrl_regs.cr0 = GUEST_CR0;
- core->ctrl_regs.cr4 = GUEST_CR4;
+#define GUEST_CR0_MASK 0x80010031
+#define GUEST_CR4_MASK 0x00002010
+ core->ctrl_regs.cr0 |= GUEST_CR0_MASK;
+ core->ctrl_regs.cr4 |= GUEST_CR4_MASK;
((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->pe = 1;
((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->wp = 1;