static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
if (header_type == 0x00) {
switch (reg_num) {
+ case 0x00:
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0b:
+ case 0x0e:
+ case 0x3d:
+ return 0;
+
+ default:
+ return 1;
+
// case (non writable reg list):
default:
// COMMAND update
} else if (cur_reg == 0x0f) {
// BIST update
+ pci_dev->config_header.BIST = 0x00;
}
}
}
int dev_num,
struct v3_pci_bar * bars,
int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
- int (*cmd_update)(struct pci_dev *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
+ int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
int (*bar_update)(struct pci_device * pci_dev, uint_t bar),
void * private_data) {
}
memset(pci_dev, 0, sizeof(struct pci_device));
-
+
pci_dev->bus_num = bus_num;
pci_dev->dev_num = dev_num;