switch (length) { \
case 1: \
mask = mask_1; \
+ break; \
case 2: \
mask = mask_2; \
+ break; \
case 4: \
mask = mask_4; \
+ break; \
case 8: \
mask = mask_8; \
+ break; \
} \
val & mask;}) \
- PrintDebug("Struct: Seg=%p, base=%p, index=%p, scale=%p, displacement=%p\n",
+ PrintDebug("Struct: Seg=%p, base=%p, index=%p, scale=%p, displacement=%p (size=%d)\n",
(void *)mem_op.segment, (void*)mem_op.base, (void *)mem_op.index,
- (void *)mem_op.scale, (void *)(addr_t)mem_op.displacement);
+ (void *)mem_op.scale, (void *)(addr_t)mem_op.displacement, mem_op.displacement_size);
PrintDebug("operand size: %d\n", operand->size);
- seg = mem_op.segment;
+ seg = MASK(mem_op.segment, mem_op.segment_size);
base = MASK(mem_op.base, mem_op.base_size);
index = MASK(mem_op.index, mem_op.index_size);
scale = mem_op.scale;
static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg, addr_t * v3_reg, uint_t * reg_len) {
+ PrintError("Xed Register: %s\n", xed_reg_enum_t2str(xed_reg));
+
switch (xed_reg) {
case XED_REG_INVALID:
*v3_reg = 0;
return GPR_REGISTER;
+
+
+
+ case XED_REG_R8:
+ *v3_reg = (addr_t)&(info->vm_regs.r8);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R8D:
+ *v3_reg = (addr_t)&(info->vm_regs.r8);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R8W:
+ *v3_reg = (addr_t)&(info->vm_regs.r8);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R8B:
+ *v3_reg = (addr_t)&(info->vm_regs.r8);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R9:
+ *v3_reg = (addr_t)&(info->vm_regs.r9);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R9D:
+ *v3_reg = (addr_t)&(info->vm_regs.r9);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R9W:
+ *v3_reg = (addr_t)&(info->vm_regs.r9);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R9B:
+ *v3_reg = (addr_t)&(info->vm_regs.r9);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R10:
+ *v3_reg = (addr_t)&(info->vm_regs.r10);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R10D:
+ *v3_reg = (addr_t)&(info->vm_regs.r10);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R10W:
+ *v3_reg = (addr_t)&(info->vm_regs.r10);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R10B:
+ *v3_reg = (addr_t)&(info->vm_regs.r10);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R11:
+ *v3_reg = (addr_t)&(info->vm_regs.r11);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R11D:
+ *v3_reg = (addr_t)&(info->vm_regs.r11);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R11W:
+ *v3_reg = (addr_t)&(info->vm_regs.r11);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R11B:
+ *v3_reg = (addr_t)&(info->vm_regs.r11);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R12:
+ *v3_reg = (addr_t)&(info->vm_regs.r12);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R12D:
+ *v3_reg = (addr_t)&(info->vm_regs.r12);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R12W:
+ *v3_reg = (addr_t)&(info->vm_regs.r12);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R12B:
+ *v3_reg = (addr_t)&(info->vm_regs.r12);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R13:
+ *v3_reg = (addr_t)&(info->vm_regs.r13);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R13D:
+ *v3_reg = (addr_t)&(info->vm_regs.r13);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R13W:
+ *v3_reg = (addr_t)&(info->vm_regs.r13);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R13B:
+ *v3_reg = (addr_t)&(info->vm_regs.r13);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R14:
+ *v3_reg = (addr_t)&(info->vm_regs.r14);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R14D:
+ *v3_reg = (addr_t)&(info->vm_regs.r14);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R14W:
+ *v3_reg = (addr_t)&(info->vm_regs.r14);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R14B:
+ *v3_reg = (addr_t)&(info->vm_regs.r14);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+ case XED_REG_R15:
+ *v3_reg = (addr_t)&(info->vm_regs.r15);
+ *reg_len = 8;
+ return GPR_REGISTER;
+ case XED_REG_R15D:
+ *v3_reg = (addr_t)&(info->vm_regs.r15);
+ *reg_len = 4;
+ return GPR_REGISTER;
+ case XED_REG_R15W:
+ *v3_reg = (addr_t)&(info->vm_regs.r15);
+ *reg_len = 2;
+ return GPR_REGISTER;
+ case XED_REG_R15B:
+ *v3_reg = (addr_t)&(info->vm_regs.r15);
+ *reg_len = 1;
+ return GPR_REGISTER;
+
+
/*
* CTRL REGS
*/
- case XED_REG_R8:
- case XED_REG_R8D:
- case XED_REG_R8W:
- case XED_REG_R8B:
-
- case XED_REG_R9:
- case XED_REG_R9D:
- case XED_REG_R9W:
- case XED_REG_R9B:
-
- case XED_REG_R10:
- case XED_REG_R10D:
- case XED_REG_R10W:
- case XED_REG_R10B:
-
- case XED_REG_R11:
- case XED_REG_R11D:
- case XED_REG_R11W:
- case XED_REG_R11B:
-
- case XED_REG_R12:
- case XED_REG_R12D:
- case XED_REG_R12W:
- case XED_REG_R12B:
-
- case XED_REG_R13:
- case XED_REG_R13D:
- case XED_REG_R13W:
- case XED_REG_R13B:
-
- case XED_REG_R14:
- case XED_REG_R14D:
- case XED_REG_R14W:
- case XED_REG_R14B:
- case XED_REG_R15:
- case XED_REG_R15D:
- case XED_REG_R15W:
- case XED_REG_R15B:
case XED_REG_XMM0:
case XED_REG_XMM1:
static v3_op_type_t get_opcode(xed_iform_enum_t iform) {
switch (iform) {
+
+ /* Control Instructions */
+
case XED_IFORM_MOV_CR_GPR64_CR:
case XED_IFORM_MOV_CR_GPR32_CR:
return V3_OP_MOVCR2;
case XED_IFORM_CLTS:
return V3_OP_CLTS;
+ case XED_IFORM_INVLPG_MEMb:
+ return V3_OP_INVLPG;
+
+
+ /* Data Instructions */
+
case XED_IFORM_ADC_MEMv_GPRv:
case XED_IFORM_ADC_MEMv_IMM:
case XED_IFORM_ADC_MEMb_GPR8:
case XED_IFORM_SETZ_MEMb:
return V3_OP_SETZ;
+
case XED_IFORM_MOVSB:
case XED_IFORM_MOVSW:
case XED_IFORM_MOVSD: