Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


Added fix to is_svm_capable() to correctly detect nested paging
[palacios.git] / palacios / src / palacios / svm.c
index cbed250..8f6d1dc 100644 (file)
@@ -9,7 +9,7 @@
 #include <palacios/vmm_debug.h>
 #include <palacios/vm_guest_mem.h>
 
-#include <palacios/vmm_emulate.h>
+#include <palacios/vmm_decoder.h>
 
 
 extern struct vmm_os_hooks * os_hooks;
@@ -154,7 +154,7 @@ static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info vm_info) {
   ctrl_area->instrs.INTR = 1;
 
 
-  if (vm_info.page_mode == SHADOW_PAGING) {
+  if (vm_info.shdw_pg_mode == SHADOW_PAGING) {
     PrintDebug("Creating initial shadow page table\n");
     vm_info.shdw_pg_state.shadow_cr3 |= ((addr_t)create_passthrough_pde32_pts(&vm_info) & ~0xfff);
     PrintDebug("Created\n");
@@ -170,12 +170,19 @@ static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info vm_info) {
     ctrl_area->instrs.INVLPG = 1;
     ctrl_area->instrs.INVLPGA = 1;
 
+    /* JRL: This is a performance killer, and a simplistic solution */
+    /* We need to fix this */
+    ctrl_area->TLB_CONTROL = 1;
+    
+
+
     guest_state->g_pat = 0x7040600070406ULL;
 
     guest_state->cr0 |= 0x80000000;
-  } else if (vm_info.page_mode == NESTED_PAGING) {
+
+  } else if (vm_info.shdw_pg_mode == NESTED_PAGING) {
     // Flush the TLB on entries/exits
-    //ctrl_area->TLB_CONTROL = 1;
+
 
     // Enable Nested Paging
     //ctrl_area->NP_ENABLE = 1;
@@ -250,15 +257,17 @@ static int start_svm_guest(struct guest_info *info) {
 
     CLGI();
 
+    PrintDebug("SVM Entry to rip=%x...\n", info->rip);
+
     rdtscll(info->time_state.cached_host_tsc);
     guest_ctrl->TSC_OFFSET = info->time_state.guest_tsc - info->time_state.cached_host_tsc;
 
     safe_svm_launch((vmcb_t*)(info->vmm_data), &(info->vm_regs));
 
     rdtscll(tmp_tsc);
-
     //PrintDebug("SVM Returned\n");
 
+
     v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
 
     STGI();
@@ -271,7 +280,6 @@ static int start_svm_guest(struct guest_info *info) {
 
       PrintDebug("SVM ERROR!!\n"); 
       
-
       PrintDebug("RIP: %x\n", guest_state->rip);
 
 
@@ -280,7 +288,13 @@ static int start_svm_guest(struct guest_info *info) {
 
       PrintDebug("RIP Linear: %x\n", linear_addr);
 
-      guest_pa_to_host_pa(info, linear_addr, &host_addr);
+      
+      if (info->mem_mode == PHYSICAL_MEM) {
+       guest_pa_to_host_pa(info, linear_addr, &host_addr);
+      } else if (info->mem_mode == VIRTUAL_MEM) {
+       guest_va_to_host_pa(info, linear_addr, &host_addr);
+      }
+
 
       PrintDebug("Host Address of rip = 0x%x\n", host_addr);
 
@@ -299,6 +313,60 @@ static int start_svm_guest(struct guest_info *info) {
 /* Checks machine SVM capability */
 /* Implemented from: AMD Arch Manual 3, sect 15.4 */ 
 int is_svm_capable() {
+
+#if 1
+  // Dinda
+
+  uint_t ret;
+  uint_t vm_cr_low = 0, vm_cr_high = 0;
+
+
+  ret =  cpuid_ecx(CPUID_FEATURE_IDS);
+  
+  PrintDebug("CPUID_FEATURE_IDS_ecx=0x%x\n",ret);
+
+  if ((ret & CPUID_FEATURE_IDS_ecx_svm_avail) == 0) {
+    PrintDebug("SVM Not Available\n");
+    return 0;
+  }  else {
+    Get_MSR(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
+    
+    PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n",vm_cr_high,vm_cr_low);
+    
+    if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
+      PrintDebug("SVM is available but is disabled.\n");
+
+      ret = cpuid_edx(CPUID_SVM_REV_AND_FEATURE_IDS);
+      
+      PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n",ret);
+      
+      if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
+       PrintDebug("SVM BIOS Disabled, not unlockable\n");
+      } else {
+       PrintDebug("SVM is locked with a key\n");
+      }
+      return 0;
+
+    } else {
+      PrintDebug("SVM is available and  enabled.\n");
+
+      ret = cpuid_edx(CPUID_SVM_REV_AND_FEATURE_IDS);
+      
+      PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n",ret);
+
+      if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
+       PrintDebug("SVM Nested Paging not supported\n");
+      } else {
+       PrintDebug("SVM Nested Paging supported\n");
+      }
+      
+      return 1;
+      
+    }
+  }
+
+#else
+
   uint_t ret =  cpuid_ecx(CPUID_FEATURE_IDS);
   uint_t vm_cr_low = 0, vm_cr_high = 0;
 
@@ -310,11 +378,19 @@ int is_svm_capable() {
 
   Get_MSR(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
 
+  PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n",vm_cr_high,vm_cr_low);
+
+
+  // this part is clearly wrong, since the np bit is in 
+  // edx, not ecx
   if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 1) {
     PrintDebug("Nested Paging not supported\n");
+  } else {
+    PrintDebug("Nested Paging supported\n");
   }
 
   if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 0) {
+    PrintDebug("SVM is disabled.\n");
     return 1;
   }
 
@@ -327,6 +403,9 @@ int is_svm_capable() {
   }
 
   return 0;
+
+#endif
+
 }