// availability
for (j = 0; j < 8; j++) {
if (!(bus->dev_map[i] & (0x1 << j))) {
- return i * 8 + j;
+ return ((i * 8) + j);
}
}
}
}
static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
- int major = dev_num / 8;
+ int major = (dev_num / 8);
int minor = dev_num % 8;
bus->dev_map[major] |= (0x1 << minor);
static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
if (header_type == 0x00) {
switch (reg_num) {
- // case (non writable reg list):
-
- default:
- return 1;
+ case 0x00:
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0b:
+ case 0x0e:
+ case 0x3d:
+ return 0;
+
+ default:
+ return 1;
+
}
} else {
// PCI to PCI Bridge = 0x01
pci_dev->bar[bar_reg].updated = 1;
}
} else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
- pci_dev->ext_rom_updated = 1;
+ pci_dev->ext_rom_update_flag = 1;
} else if (cur_reg == 0x04) {
// COMMAND update
uint8_t command = *((uint8_t *)src + i);
if (pci_dev->cmd_update) {
pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
}
-
+
+
} else if (cur_reg == 0x0f) {
// BIST update
+ pci_dev->config_header.BIST = 0x00;
}
}
}
if (pci_dev->bar[i].updated) {
int bar_offset = 0x10 + 4 * i;
- *(uint32_t *)pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
+ *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
if (pci_dev->bar[i].bar_update) {
pci_dev->bar[i].bar_update(pci_dev, i);
static int init_i440fx(struct vm_device * dev) {
- struct pci_device * pci_dev = v3_pci_register_device(dev, 0, "i440FX", 0,
- NULL, NULL, NULL);
+ struct pci_device * pci_dev = NULL;
+ struct v3_pci_bar bars[6];
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ bars[i].type = PCI_BAR_NONE;
+ bars[i].mem_hook = 0;
+ bars[i].num_pages = 0;
+ bars[i].bar_update = NULL;
+ }
+
+ pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "i440FX", 0, bars,
+ NULL, NULL, NULL, NULL);
if (!pci_dev) {
- return -1;
+ return -1;
}
pci_dev->config_header.vendor_id = 0x8086;
pci_dev->config_header.revision = 0x0002;
pci_dev->config_header.subclass = 0x00; // SubClass: host2pci
pci_dev->config_header.class = 0x06; // Class: PCI bridge
- pci_dev->config_header.header_type = 0x00;
pci_dev->bus_num = 0;
-
return 0;
}
+/*
+static void test_devices(struct vm_device * dev) {
+ struct pci_device * pci_dev = NULL;
+ struct v3_pci_bar bars[6];
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ bars[i].type = PCI_BAR_NONE;
+ bars[i].mem_hook = 0;
+ bars[i].num_pages = 0;
+ bars[i].bar_update = NULL;
+ }
+
+
+ pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "", 0, bars,
+ NULL, NULL, NULL, NULL);
+
+ pci_dev->config_header.vendor_id = 0x8086;
+ pci_dev->config_header.device_id = 0x0101;
+ pci_dev->config_header.revision = 0x0002;
+ pci_dev->config_header.subclass = 0x01; // SubClass: host2pci
+ pci_dev->config_header.class = 0x01; // Class: PCI bridge
+
+ pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "", 0, bars,
+ NULL, NULL, NULL, NULL);
+
+ pci_dev->config_header.vendor_id = 0x8086;
+ pci_dev->config_header.device_id = 0x0101;
+ pci_dev->config_header.revision = 0x0002;
+ pci_dev->config_header.subclass = 0x00; // SubClass: host2pci
+ pci_dev->config_header.class = 0x02; // Class: PCI bridge
+
+
+
+
+}
+
+*/
static void init_pci_busses(struct pci_internal * pci_state) {
int i;
return -1;
}
- PrintDebug("Sizeof config header=%d\n", sizeof(struct pci_config_header));
+ //test_devices(dev);
+
+ PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
for (i = 0; i < 4; i++) {
v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
int bar_offset = 0x10 + 4 * i;
if (pci_dev->bar[i].type == PCI_BAR_IO) {
+ //pci_dev->bar[i].mask = 0x0000fffd;
+ pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_io_ports) - 1)) | 0x01;
+
*(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000001;
} else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
- pci_dev->bar[i].mask = (pci_dev->bar[i].num_pages << 12) - 1;
+ pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
*(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000008;
PrintError("Invalid BAR type for bar #%d\n", i);
return -1;
}
-
-
}
-}
+ return 0;
+}
// if dev_num == -1, auto assign
struct pci_device * v3_pci_register_device(struct vm_device * pci,
+ pci_device_type_t dev_type,
uint_t bus_num,
const char * name,
int dev_num,
struct v3_pci_bar * bars,
int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
- int (*bar_update)(struct pci_device * pci_dev, uint_t bar),
+ int (*ext_rom_update)(struct pci_device * pci_dev),
void * private_data) {
struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
}
memset(pci_dev, 0, sizeof(struct pci_device));
-
+
+ switch (dev_type) {
+ case PCI_STD_DEVICE:
+ pci_dev->config_header.header_type = 0x00;
+ break;
+ default:
+ PrintError("Unhandled PCI Device Type: %d\n", dev_type);
+ return NULL;
+ }
+
pci_dev->bus_num = bus_num;
pci_dev->dev_num = dev_num;
// register update callbacks
pci_dev->config_update = config_update;
- pci_dev->bar_update = bar_update;
+ pci_dev->cmd_update = cmd_update;
+ pci_dev->ext_rom_update = ext_rom_update;
pci_dev->priv_data = private_data;
-
+
//copy bars
for (i = 0; i < 6; i ++){
- pci_dev->bar[i].type = bars[i].type;
- pci_dev->bar[i].num_resources = bars[i].num_resources;
- pci_dev->bar[i].bar_update = bars[i].bar_update;
+ pci_dev->bar[i].type = bars[i].type;
+
+ if (pci_dev->bar[i].type == PCI_BAR_IO) {
+ pci_dev->bar[i].num_io_ports = bars[i].num_io_ports;
+ } else {
+ pci_dev->bar[i].num_pages = bars[i].num_pages;
+ }
+
+ pci_dev->bar[i].mem_hook = bars[i].mem_hook;
+ pci_dev->bar[i].bar_update = bars[i].bar_update;
}
if (init_bars(pci_dev) == -1) {
return NULL;
}
- pci_dev->cmd_update = cmd_update;
- pci_dev->ext_rom_update = ext_rom_update;
-
// add the device
add_device_to_bus(bus, pci_dev);
-
#ifdef DEBUG_PCI
pci_dump_state(pci_state);
#endif
