struct ide_drive {
// Command Registers
- uint8_t data_port; // 0x1f0,0x170
- struct ide_error_reg error_reg; // [read] 0x1f1,0x171
+
+ ide_dev_type_t drive_type;
+
+
uint8_t sector_count; // 0x1f2,0x172
uint8_t sector_num; // 0x1f3,0x173
-
union {
uint16_t cylinder;
struct {
} __attribute__((packed));
} __attribute__((packed));
- struct ide_drive_head_reg drive_head; // 0x1f6,0x176
-
- struct ide_status_reg status; // [read] 0x1f7,0x177
- uint8_t command_reg; // [write] 0x1f7,0x177
-
- // Control Registers
- struct ide_drive_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
+};
- ide_dev_type_t drive_type;
+struct ide_channel {
+ struct ide_drive drives[2];
-};
+ // Command Registers
+ struct ide_error_reg error_reg; // [read] 0x1f1,0x171
+ struct ide_features_reg features;
+ struct ide_drive_head_reg drive_head; // 0x1f6,0x176
-struct ide_channel {
- struct ide_drive drives[2];
+ struct ide_status_reg status; // [read] 0x1f7,0x177
+ uint8_t command_reg; // [write] 0x1f7,0x177
- int drive_sel;
+ // Control Registers
+ struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
};
}
static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
- return &(channel->drives[channel->drive_sel]);
+ return &(channel->drives[channel->drive_head.drive_sel]);
+}
+
+
+static inline int is_lba_enabled(struct ide_channel * channel) {
+ return channel->drive_head.lba_mode;
+}
+
+
+static void drive_reset(struct ide_drive * drive) {
+ drive->sector_count = 0x01;
+ drive->sector_num = 0x01;
+
+ if (drive->drive_type == IDE_CDROM) {
+ drive->cylinder = 0xeb14;
+ } else {
+ drive->cylinder = 0x0000;
+ }
+
+ // Send the reset signal to the connected device callbacks
+ // channel->drives[0].reset();
+ // channel->drives[1].reset();
+}
+
+static void channel_reset(struct ide_channel * channel) {
+
+ // set busy and seek complete flags
+ channel->status.val = 0x90;
+
+ // Clear errors
+ channel->error_reg.val = 0x01;
+
+ // clear commands
+ channel->command_reg = 0x00;
+
+ channel->ctrl_reg.irq_enable = 0;
+}
+
+static void channel_reset_complete(struct ide_channel * channel) {
+ channel->status.busy = 0;
+ channel->status.ready = 1;
+
+ channel->drive_head.head_num = 0;
+
+ drive_reset(&(channel->drives[0]));
+ drive_reset(&(channel->drives[1]));
}
}
static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
+ struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
+ struct ide_channel * channel = get_selected_channel(ide, port);
+ struct ide_drive * drive = get_selected_drive(channel);
+
+ if (length != 1) {
+ PrintError("Invalid Write length on IDE port %x\n", port);
+ return -1;
+ }
+
PrintDebug("IDE: Writing Standard Port %x (val=%x)\n", port, *(uint8_t *)src);
- return -1;
+
+
+ switch (port) {
+ // reset and interrupt enable
+ case PRI_CTRL_PORT:
+ case SEC_CTRL_PORT: {
+ struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
+
+ // only reset channel on a 0->1 reset bit transition
+ if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
+ channel_reset(channel);
+ } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
+ channel_reset_complete(channel);
+ }
+
+ channel->ctrl_reg.val = tmp_ctrl->val;
+ break;
+ }
+ case PRI_FEATURES_PORT:
+ case SEC_FEATURES_PORT:
+ channel->features.val = *(uint8_t *)src;
+ break;
+
+ case PRI_SECT_CNT_PORT:
+ case SEC_SECT_CNT_PORT:
+ drive->sector_count = *(uint8_t *)src;
+ break;
+
+ case PRI_SECT_NUM_PORT:
+ case SEC_SECT_NUM_PORT:
+ drive->sector_num = *(uint8_t *)src;
+
+ case PRI_CYL_LOW_PORT:
+ case SEC_CYL_LOW_PORT:
+ drive->cylinder_low = *(uint8_t *)src;
+ break;
+
+ case PRI_CYL_HIGH_PORT:
+ case SEC_CYL_HIGH_PORT:
+ drive->cylinder_high = *(uint8_t *)src;
+ break;
+
+ case PRI_DRV_SEL_PORT:
+ case SEC_DRV_SEL_PORT: {
+ channel->drive_head.val = *(uint8_t *)src;
+
+ // make sure the reserved bits are ok..
+ // JRL TODO: check with new ramdisk to make sure this is right...
+ channel->drive_head.val |= 0xa0;
+
+ drive = get_selected_drive(channel);
+
+ // Selecting a non-present device is a no-no
+ if (drive->drive_type == IDE_NONE) {
+ PrintDebug("Attempting to select a non-present drive\n");
+ channel->error_reg.abort = 1;
+ channel->status.error = 1;
+ }
+
+ break;
+ }
+ default:
+ PrintError("IDE: Write to unknown Port %x\n", port);
+ return -1;
+ }
+ return length;
}
// This is really the error register.
case PRI_FEATURES_PORT:
case SEC_FEATURES_PORT:
- *(uint8_t *)dst = drive->error_reg.val;
+ *(uint8_t *)dst = channel->error_reg.val;
break;
case PRI_SECT_CNT_PORT:
case PRI_DRV_SEL_PORT:
case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
- *(uint8_t *)dst = drive->drive_head.val;
+ *(uint8_t *)dst = channel->drive_head.val;
break;
case PRI_CTRL_PORT:
case PRI_CMD_PORT:
case SEC_CMD_PORT:
// Something about lowering interrupts here....
- *(uint8_t *)dst = drive->status.val;
+ *(uint8_t *)dst = channel->status.val;
break;
default:
static void init_drive(struct ide_drive * drive) {
- drive->data_port = 0x00;
- drive->error_reg.val = 0x01;
+
drive->sector_count = 0x01;
drive->sector_num = 0x01;
drive->cylinder = 0x0000;
- drive->drive_head.val = 0x00;
-
- drive->status.val = 0x00;
- drive->command_reg = 0x00;
- drive->ctrl_reg.val = 0x08;
drive->drive_type = IDE_NONE;
static void init_channel(struct ide_channel * channel) {
int i = 0;
+ channel->error_reg.val = 0x01;
+ channel->drive_head.val = 0x00;
+ channel->status.val = 0x00;
+ channel->command_reg = 0x00;
+ channel->ctrl_reg.val = 0x08;
+
for (i = 0; i < 2; i++) {
init_drive(&(channel->drives[i]));
}
- channel->drive_sel = 0;
}
static void init_ide_state(struct ide_internal * ide) {
