#include <palacios/vm_guest_mem.h>
#include <devices/ide.h>
#include <devices/pci.h>
+#include <devices/southbridge.h>
#include "ide-types.h"
#include "atapi-types.h"
+#ifndef DEBUG_IDE
+#undef PrintDebug
+#define PrintDebug(fmt, args...)
+#endif
+
#define PRI_DEFAULT_IRQ 14
#define SEC_DEFAULT_IRQ 15
#define PRI_DEFAULT_DMA_PORT 0xc000
#define SEC_DEFAULT_DMA_PORT 0xc008
-
#define DATA_BUFFER_SIZE 2048
static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
struct ide_hd_state {
int accessed;
+
+ /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
+ uint_t mult_sector_num;
+
+ /* This is the current op sector size:
+ * for multiple sector ops this equals mult_sector_num
+ * for standard ops this equals 1
+ */
+ uint_t cur_sector_num;
};
struct ide_drive {
int irq; // this is temporary until we add PCI support
- struct pci_device * pci_dev;
-
// Control Registers
struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
struct ide_internal {
struct ide_channel channels[2];
- struct vm_device * pci;
- struct pci_device * busmaster_pci;
+
+ struct v3_southbridge * southbridge;
+ struct vm_device * pci_bus;
+
+ struct pci_device * ide_pci;
};
uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
int ret;
-
PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
return -1;
}
- channel->status.busy = 0;
- channel->status.ready = 1;
- channel->status.data_req = 0;
- channel->status.error = 0;
- channel->status.seek_complete = 1;
+
/*
drive->irq_flags.io_dir = 1;
// set DMA status
- channel->dma_status.active = 0;
- channel->dma_status.err = 1;
- channel->dma_status.int_gen = 1;
+
+ if (prd_entry.end_of_table) {
+ channel->dma_status.active = 0;
+ channel->dma_status.err = 0;
+ channel->dma_status.int_gen = 1;
+
+ channel->status.busy = 0;
+ channel->status.ready = 1;
+ channel->status.data_req = 0;
+ channel->status.error = 0;
+ channel->status.seek_complete = 1;
+ }
ide_raise_irq(dev, channel);
}
-/*
- * This is an ugly ugly ugly way to differentiate between the first and second DMA channels
- */
-
-static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel);
-static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel);
-
-
-static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
- PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
- return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0]));
-}
-
-static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
- PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
- return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1]));
-}
-
-
-static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
- PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
- return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0]));
-}
-
-static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
- PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
- return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1]));
-}
-
#define DMA_CMD_PORT 0x00
#define DMA_STATUS_PORT 0x02
#define DMA_PRD_PORT2 0x06
#define DMA_PRD_PORT3 0x07
+#define DMA_CHANNEL_FLAG 0x08
-static int write_dma_port(ushort_t port_offset, void * src, uint_t length,
- struct vm_device * dev, struct ide_channel * channel) {
+static int write_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
+ struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
+ uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
+ uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
+ struct ide_channel * channel = &(ide->channels[channel_flag]);
switch (port_offset) {
case DMA_CMD_PORT:
return -1;
}
}
+
+ channel->dma_cmd.val &= 0x09;
}
break;
}
-static int read_dma_port(ushort_t port_offset, void * dst, uint_t length,
- struct vm_device * dev, struct ide_channel * channel) {
+static int read_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
+ struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
+ uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
+ uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
+ struct ide_channel * channel = &(ide->channels[channel_flag]);
switch (port_offset) {
case DMA_CMD_PORT:
case 0x20: // Read Sectors with Retry
case 0x21: // Read Sectors without Retry
+ drive->hd_state.cur_sector_num = 1;
+
if (ata_read_sectors(dev, channel) == -1) {
PrintError("Error reading sectors\n");
return -1;
break;
case 0x24: // Read Sectors Extended
+ drive->hd_state.cur_sector_num = 1;
+
if (ata_read_sectors_ext(dev, channel) == -1) {
PrintError("Error reading extended sectors\n");
return -1;
}
break;
+
+ case 0xc8: // Read DMA with retry
+ case 0xc9: // Read DMA
+ drive->hd_state.cur_sector_num = 1;
+
+ break;
case 0xef: // Set Features
// Prior to this the features register has been written to.
// This command tells the drive to check if the new value is supported (the value is drive specific)
ide_raise_irq(dev, channel);
break;
+ case 0x91: // Initialize Drive Parameters
+ case 0x10: // recalibrate?
+ channel->status.error = 0;
+ channel->status.ready = 1;
+ channel->status.seek_complete = 1;
+ ide_raise_irq(dev, channel);
+ break;
+ case 0xc6: { // Set multiple mode (IDE Block mode)
+ // This makes the drive transfer multiple sectors before generating an interrupt
+ uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
+
+ if (tmp_sect_num > MAX_MULT_SECTORS) {
+ ide_abort_command(dev, channel);
+ break;
+ }
+
+ if (drive->sector_count == 0) {
+ drive->hd_state.mult_sector_num= 1;
+ } else {
+ drive->hd_state.mult_sector_num = drive->sector_count;
+ }
+
+ channel->status.ready = 1;
+ channel->status.error = 0;
+
+ ide_raise_irq(dev, channel);
+
+ break;
+ }
+ case 0xc4: // read multiple sectors
+ drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
default:
PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
return -1;
if ((data_offset == 0) && (drive->transfer_index > 0)) {
drive->current_lba++;
- if (ata_read(dev, channel) == -1) {
+ if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
PrintError("Could not read next disk sector\n");
return -1;
}
drive->transfer_index += length;
- if ((drive->transfer_index % IDE_SECTOR_SIZE) == 0) {
+
+ /* This is the trigger for interrupt injection.
+ * For read single sector commands we interrupt after every sector
+ * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
+ * cur_sector_num is configured depending on the operation we are currently running
+ * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
+ */
+ if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
+ (drive->transfer_index == drive->transfer_length)) {
if (drive->transfer_index < drive->transfer_length) {
// An increment is complete, but there is still more data to be transferred...
PrintDebug("Integral Complete, still transferring more sectors\n");
static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
- PrintDebug("Interupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
+ PrintDebug("PCI Config Update\n");
+ PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
return 0;
}
static int init_ide_state(struct vm_device * dev) {
struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
- struct v3_pci_bar bars[6];
- struct pci_device * pci_dev = NULL;
- int i, j;
+ int i;
- for (i = 0; i < 2; i++) {
+ /*
+ * Check if the PIIX 3 actually represents both IDE channels in a single PCI entry
+ */
+
+ for (i = 0; i < 1; i++) {
init_channel(&(ide->channels[i]));
// JRL: this is a terrible hack...
ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
-
- for (j = 0; j < 6; j++) {
- bars[j].type = PCI_BAR_NONE;
- }
-
-
- bars[4].type = PCI_BAR_IO;
- bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8);
- bars[4].num_ports = 8;
-
- if (i == 0) {
- bars[4].io_read = read_pri_dma_port;
- bars[4].io_write = write_pri_dma_port;
- } else {
- bars[4].io_read = read_sec_dma_port;
- bars[4].io_write = write_sec_dma_port;
- }
-
- pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
- pci_config_update, NULL, NULL, dev);
-
- if (pci_dev == NULL) {
- PrintError("Failed to register IDE BUS %d with PCI\n", i);
- return -1;
- }
-
- ide->channels[i].pci_dev = pci_dev;
-
- pci_dev->config_header.vendor_id = 0x1095;
- pci_dev->config_header.device_id = 0x0646;
- pci_dev->config_header.revision = 0x8f07;
- pci_dev->config_header.subclass = 0x01;
- pci_dev->config_header.class = 0x01;
-
- pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i;
- pci_dev->config_header.intr_pin = 1;
- }
-
-
-
- /* Register PIIX3 Busmaster PCI device */
- for (j = 0; j < 6; j++) {
- bars[j].type = PCI_BAR_NONE;
}
- pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars,
- NULL, NULL, NULL, dev);
-
-
- ide->busmaster_pci = pci_dev;
-
- pci_dev->config_header.vendor_id = 0x8086;
- pci_dev->config_header.device_id = 0x7010;
- pci_dev->config_header.revision = 0x80;
- pci_dev->config_header.subclass = 0x01;
- pci_dev->config_header.class = 0x01;
-
return 0;
}
static int init_ide(struct vm_device * dev) {
- //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
+ struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
PrintDebug("IDE: Initializing IDE\n");
v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
&read_port_std, &write_port_std);
+
+
+
+ if (ide->pci_bus) {
+ struct v3_pci_bar bars[6];
+ struct v3_southbridge * southbridge = (struct v3_southbridge *)(ide->southbridge);
+ struct pci_device * sb_pci = (struct pci_device *)(southbridge->southbridge_pci);
+ struct pci_device * pci_dev = NULL;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ bars[i].type = PCI_BAR_NONE;
+ }
+
+ bars[4].type = PCI_BAR_IO;
+ bars[4].default_base_port = PRI_DEFAULT_DMA_PORT;
+ bars[4].num_ports = 16;
+
+ bars[4].io_read = read_dma_port;
+ bars[4].io_write = write_dma_port;
+
+ pci_dev = v3_pci_register_device(ide->pci_bus, PCI_STD_DEVICE, 0, sb_pci->dev_num, 1,
+ "PIIX3_IDE", bars,
+ pci_config_update, NULL, NULL, dev);
+
+ if (pci_dev == NULL) {
+ PrintError("Failed to register IDE BUS %d with PCI\n", i);
+ return -1;
+ }
+
+ /* This is for CMD646 devices
+ pci_dev->config_header.vendor_id = 0x1095;
+ pci_dev->config_header.device_id = 0x0646;
+ pci_dev->config_header.revision = 0x8f07;
+ */
+
+ pci_dev->config_header.vendor_id = 0x8086;
+ pci_dev->config_header.device_id = 0x7010;
+ pci_dev->config_header.revision = 0x8000;
+
+ pci_dev->config_header.subclass = 0x01;
+ pci_dev->config_header.class = 0x01;
+
+ pci_dev->config_header.command = 0;
+ pci_dev->config_header.status = 0x0280;
+ }
+
return 0;
}
};
-struct vm_device * v3_create_ide(struct vm_device * pci) {
+struct vm_device * v3_create_ide(struct vm_device * pci_bus, struct vm_device * southbridge_dev) {
struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
- ide->pci = pci;
+ ide->pci_bus = pci_bus;
+ ide->southbridge = (struct v3_southbridge *)(southbridge_dev->private_data);
PrintDebug("IDE: Creating IDE bus x 2\n");
drive->drive_type = IDE_DISK;
drive->hd_state.accessed = 0;
+ drive->hd_state.mult_sector_num = 1;
drive->hd_ops = ops;
