clean up

[palacios.git] / palacios / src / devices / 8259a.c

diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c
index deabacd..b636ddc 100644 (file)
--- a/palacios/src/devices/8259a.c
+++ b/palacios/src/devices/8259a.c
@@ -6,8 +6,10 @@
 #ifndef DEBUG_PIC
 #undef PrintDebug
 #define PrintDebug(fmt, args...)
+#define PrintPicTrace(_f, _a...) PrintTrace("\n8259a.c(%d) "_f, __LINE__, ## _a)
 #endif
 
+
 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4,  READY} pic_state_t;
 
 static const uint_t MASTER_PORT1 = 0x20;
@@ -181,6 +183,32 @@ static int pic_raise_intr(void * private_data, int irq) {
   return 0;
 }
 
+
+/*Zheng 07/30/2008*/
+
+static int pic_lower_intr(void *private_data, int irq_no) {
+
+  struct pic_internal *state = (struct pic_internal*)private_data;
+
+  PrintPicTrace("[pic_lower_intr] IRQ line %d now low\n", (unsigned) irq_no);
+  if (irq_no <= 7) {
+
+    state->master_irr &= ~(1 << irq_no);
+    if ((state->master_irr & ~(state->master_imr)) == 0) {
+      PrintPicTrace("\t\tFIXME: Master maybe should do sth\n");
+    }
+  } else if ((irq_no > 7) && (irq_no <= 15)) {
+
+    state->slave_irr &= ~(1 << (irq_no - 8));
+    if ((state->slave_irr & (~(state->slave_imr))) == 0) {
+      PrintPicTrace("\t\tFIXME: Slave maybe should do sth\n");
+    }
+  }
+  return 0;
+}
+
+
+
 static int pic_intr_pending(void * private_data) {
   struct pic_internal * state = (struct pic_internal*)private_data;
 
@@ -193,9 +221,9 @@ static int pic_intr_pending(void * private_data) {
 }
 
 static int pic_get_intr_number(void * private_data) {
-  struct pic_internal * state = (struct pic_internal*)private_data;
-  int i=0;
-  int irq=-1;
+  struct pic_internal * state = (struct pic_internal *)private_data;
+  int i = 0;
+  int irq = -1;
 
   PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
   PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
@@ -221,11 +249,11 @@ static int pic_get_intr_number(void * private_data) {
     }
   }
 
-  if (i==15 || i==6) { 
+  if ((i == 15) || (i == 6)) { 
     DumpPICState(state);
   }
   
-  if (i==16) { 
+  if (i == 16) { 
     return -1;
   } else {
     return irq;
@@ -268,11 +296,15 @@ static int pic_end_irq(void * private_data, int irq) {
 }
 */
 
+
+/*Zheng 07/30/2008*/
 static struct intr_ctrl_ops intr_ops = {
   .intr_pending = pic_intr_pending,
   .get_intr_number = pic_get_intr_number,
   .raise_intr = pic_raise_intr,
   .begin_irq = pic_begin_irq,
+  .lower_intr = pic_lower_intr, //Zheng added
+
 };
 
 
@@ -348,12 +380,17 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic
   struct pic_internal * state = (struct pic_internal*)dev->private_data;
   uchar_t cw = *(uchar_t *)src;
 
+  PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
+
   if (length != 1) {
     PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
     return -1;
   }
   
   if (IS_ICW1(cw)) {
+
+    PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
+    
     state->master_icw1 = cw;
     state->master_state = ICW2;
 
@@ -362,6 +399,7 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic
       // handle the EOI here
       struct ocw2 * cw2 =  (struct ocw2*)&cw;
 
+      PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
       
       if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
        // specific EOI;
@@ -384,6 +422,7 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic
 
       state->master_ocw2 = cw;
     } else if (IS_OCW3(cw)) {
+      PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
       state->master_ocw3 = cw;
     } else {
       PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
@@ -403,6 +442,8 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic
     struct pic_internal * state = (struct pic_internal*)dev->private_data;
     uchar_t cw = *(uchar_t *)src;    
 
+    PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
+  
     if (length != 1) {
       PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
       return -1;
@@ -425,6 +466,8 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic
     } else if (state->master_state == ICW3) {
       struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
 
+      PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
+
       state->master_icw3 = cw;
 
       if (cw1->ic4 == 1) {
@@ -434,9 +477,11 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic
       }
 
     } else if (state->master_state == ICW4) {
+      PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
       state->master_icw4 = cw;
       state->master_state = READY;
     } else if (state->master_state == READY) {
+      PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
       state->master_imr = cw;
     } else {
       // error
@@ -451,6 +496,8 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device
   struct pic_internal * state = (struct pic_internal*)dev->private_data;
   uchar_t cw = *(uchar_t *)src;
 
+  PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
+
   if (length != 1) {
     // error
     PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
@@ -458,12 +505,15 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device
   }
 
   if (IS_ICW1(cw)) {
+    PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
     state->slave_icw1 = cw;
     state->slave_state = ICW2;
   } else if (state->slave_state == READY) {
     if (IS_OCW2(cw)) {
       // handle the EOI here
       struct ocw2 * cw2 =  (struct ocw2 *)&cw;
+
+      PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
       
       if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
        // specific EOI;
@@ -487,6 +537,7 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device
       state->slave_ocw2 = cw;
     } else if (IS_OCW3(cw)) {
       // Basically sets the IRR/ISR read flag
+      PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
       state->slave_ocw3 = cw;
     } else {
       PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
@@ -504,6 +555,8 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device
     struct pic_internal * state = (struct pic_internal*)dev->private_data;
     uchar_t cw = *(uchar_t *)src;    
 
+    PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
+
     if (length != 1) {
       PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
       return -1;
@@ -512,6 +565,8 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device
     if (state->slave_state == ICW2) {
       struct icw1 * cw1 =  (struct icw1 *)&(state->master_icw1);
 
+      PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
+
       state->slave_icw2 = cw;
 
       if (cw1->sngl == 0) {
@@ -525,6 +580,8 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device
     } else if (state->slave_state == ICW3) {
       struct icw1 * cw1 =  (struct icw1 *)&(state->master_icw1);
 
+      PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
+
       state->slave_icw3 = cw;
 
       if (cw1->ic4 == 1) {
@@ -534,9 +591,11 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device
       }
 
     } else if (state->slave_state == ICW4) {
+      PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
       state->slave_icw4 = cw;
       state->slave_state = READY;
     } else if (state->slave_state == READY) {
+      PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
       state->slave_imr = cw;
     } else {
       PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");