#include <palacios/vmm_types.h>
#include <palacios/vmm.h>
#include <palacios/vmm_dev_mgr.h>
+#include <palacios/vm_guest.h>
-#ifndef CONFIG_DEBUG_PIC
+#ifndef V3_CONFIG_DEBUG_PIC
#undef PrintDebug
#define PrintDebug(fmt, args...)
#endif
struct pic_internal {
- uchar_t master_irr;
- uchar_t slave_irr;
+ uint8_t master_irr;
+ uint8_t slave_irr;
- uchar_t master_isr;
- uchar_t slave_isr;
+ uint8_t master_isr;
+ uint8_t slave_isr;
- uchar_t master_elcr;
- uchar_t slave_elcr;
- uchar_t master_elcr_mask;
- uchar_t slave_elcr_mask;
+ uint8_t master_elcr;
+ uint8_t slave_elcr;
+ uint8_t master_elcr_mask;
+ uint8_t slave_elcr_mask;
- uchar_t master_icw1;
- uchar_t master_icw2;
- uchar_t master_icw3;
- uchar_t master_icw4;
+ uint8_t master_icw1;
+ uint8_t master_icw2;
+ uint8_t master_icw3;
+ uint8_t master_icw4;
- uchar_t slave_icw1;
- uchar_t slave_icw2;
- uchar_t slave_icw3;
- uchar_t slave_icw4;
+ uint8_t slave_icw1;
+ uint8_t slave_icw2;
+ uint8_t slave_icw3;
+ uint8_t slave_icw4;
- uchar_t master_imr;
- uchar_t slave_imr;
- uchar_t master_ocw2;
- uchar_t master_ocw3;
- uchar_t slave_ocw2;
- uchar_t slave_ocw3;
+ uint8_t master_imr;
+ uint8_t slave_imr;
+ uint8_t master_ocw2;
+ uint8_t master_ocw3;
+ uint8_t slave_ocw2;
+ uint8_t slave_ocw3;
pic_state_t master_state;
pic_state_t slave_state;
+
+ struct guest_info * core;
+
+
+ void * router_handle;
+ void * controller_handle;
};
return -1;
}
- v3_interrupt_cpu(vm, 0);
+#ifdef V3_CONFIG_MULTITHREAD_OS
+ v3_interrupt_cpu(vm, 0, 0);
+#endif
return 0;
}
for (i = 0; i < 16; i++) {
if (i <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
+ if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
//state->master_isr |= (0x1 << i);
// reset the irr
//state->master_irr &= ~(0x1 << i);
break;
}
} else {
- if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
+ if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
//state->slave_isr |= (0x1 << (i - 8));
//state->slave_irr &= ~(0x1 << (i - 8));
PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
- irq= (i - 8) + state->slave_icw2;
+ irq = (i - 8) + state->slave_icw2;
break;
}
}
}
+#if 1
if ((i == 15) || (i == 6)) {
DumpPICState(state);
}
+#endif
if (i == 16) {
return -1;
} else {
+ PrintDebug("8259 PIC: get num is returning %d\n",irq);
return irq;
}
}
}
if (irq <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
+ // This should always be true: See pic_get_intr_number
+ if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) {
state->master_isr |= (0x1 << irq);
if (!(state->master_elcr & (0x1 << irq))) {
state->master_irr &= ~(0x1 << irq);
}
+ } else {
+ PrintDebug("8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n",irq);
}
+
} else {
- state->slave_isr |= (0x1 << (irq - 8));
+ // This should always be true: See pic_get_intr_number
+ if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) {
+ state->slave_isr |= (0x1 << (irq - 8));
+
+ if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
+ state->slave_irr &= ~(0x1 << (irq - 8));
+ }
+ } else {
+ PrintDebug("8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n",irq);
+ }
- if (!(state->slave_elcr & (0x1 << irq))) {
- state->slave_irr &= ~(0x1 << (irq - 8));
- }
}
return 0;
};
-static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
}
if ((state->master_ocw3 & 0x03) == 0x02) {
- *(uchar_t *)dst = state->master_irr;
+ *(uint8_t *)dst = state->master_irr;
} else if ((state->master_ocw3 & 0x03) == 0x03) {
- *(uchar_t *)dst = state->master_isr;
+ *(uint8_t *)dst = state->master_isr;
} else {
- *(uchar_t *)dst = 0;
+ *(uint8_t *)dst = 0;
}
return 1;
}
-static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
return -1;
}
- *(uchar_t *)dst = state->master_imr;
+ *(uint8_t *)dst = state->master_imr;
return 1;
}
-static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
}
if ((state->slave_ocw3 & 0x03) == 0x02) {
- *(uchar_t*)dst = state->slave_irr;
+ *(uint8_t*)dst = state->slave_irr;
} else if ((state->slave_ocw3 & 0x03) == 0x03) {
- *(uchar_t *)dst = state->slave_isr;
+ *(uint8_t *)dst = state->slave_isr;
} else {
- *(uchar_t *)dst = 0;
+ *(uint8_t *)dst = 0;
}
return 1;
}
-static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
return -1;
}
- *(uchar_t *)dst = state->slave_imr;
+ *(uint8_t *)dst = state->slave_imr;
return 1;
}
-static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
- uchar_t cw = *(uchar_t *)src;
+static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
+ uint8_t cw = *(uint8_t *)src;
PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
}
}
PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
- } else {
+ } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) {
+ PrintDebug("8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level);
+ } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) {
+ PrintDebug("8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level);
+ } else {
PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
return -1;
}
return 1;
}
-static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
- uchar_t cw = *(uchar_t *)src;
+static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
+ uint8_t cw = *(uint8_t *)src;
PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
return 1;
}
-static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
- uchar_t cw = *(uchar_t *)src;
+static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
+ uint8_t cw = *(uint8_t *)src;
PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
return 1;
}
-static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
- uchar_t cw = *(uchar_t *)src;
+static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
+ uint8_t cw = *(uint8_t *)src;
PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
-static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("ELCR read of invalid length %d\n", length);
}
-static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("ELCR read of invalid length %d\n", length);
+static int pic_free(struct pic_internal * state) {
+ struct guest_info * core = state->core;
+
+ v3_remove_intr_controller(core, state->controller_handle);
+ v3_remove_intr_router(core->vm_info, state->router_handle);
+
+ V3_Free(state);
+ return 0;
+}
+
+#ifdef V3_CONFIG_CHECKPOINT
+static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct pic_internal * pic = (struct pic_internal *)private_data;
+
+ v3_chkpt_save_8(ctx, "MASTER_IRR", &(pic->master_irr));
+ v3_chkpt_save_8(ctx, "SLAVE_IRR", &(pic->slave_irr));
+
+ v3_chkpt_save_8(ctx, "MASTER_ISR", &(pic->master_isr));
+ v3_chkpt_save_8(ctx, "SLAVE_ISR", &(pic->slave_isr));
+
+ v3_chkpt_save_8(ctx, "MASTER_ELCR", &(pic->master_elcr));
+ v3_chkpt_save_8(ctx, "SLAVE_ELCR", &(pic->slave_elcr));
+ v3_chkpt_save_8(ctx, "MASTER_ELCR_MASK", &(pic->master_elcr_mask));
+ v3_chkpt_save_8(ctx, "SLAVE_ELCR_MASK", &(pic->slave_elcr_mask));
+
+ v3_chkpt_save_8(ctx, "MASTER_ICW1", &(pic->master_icw1));
+ v3_chkpt_save_8(ctx, "MASTER_ICW2", &(pic->master_icw2));
+ v3_chkpt_save_8(ctx, "MASTER_ICW3", &(pic->master_icw3));
+ v3_chkpt_save_8(ctx, "MASTER_ICW4", &(pic->master_icw4));
+
+ v3_chkpt_save_8(ctx, "SLAVE_ICW1", &(pic->slave_icw1));
+ v3_chkpt_save_8(ctx, "SLAVE_ICW2", &(pic->slave_icw2));
+ v3_chkpt_save_8(ctx, "SLAVE_ICW3", &(pic->slave_icw3));
+ v3_chkpt_save_8(ctx, "SLAVE_ICW4", &(pic->slave_icw4));
-static int pic_free(struct vm_device * dev) {
- v3_dev_unhook_io(dev, MASTER_PORT1);
- v3_dev_unhook_io(dev, MASTER_PORT2);
- v3_dev_unhook_io(dev, SLAVE_PORT1);
- v3_dev_unhook_io(dev, SLAVE_PORT2);
+ v3_chkpt_save_8(ctx, "MASTER_IMR", &(pic->master_imr));
+ v3_chkpt_save_8(ctx, "SLAVE_IMR", &(pic->slave_imr));
+ v3_chkpt_save_8(ctx, "MASTER_OCW2", &(pic->master_ocw2));
+ v3_chkpt_save_8(ctx, "MASTER_OCW3", &(pic->master_ocw3));
+ v3_chkpt_save_8(ctx, "SLAVE_OCW2", &(pic->slave_ocw2));
+ v3_chkpt_save_8(ctx, "SLAVE_OCW3", &(pic->slave_ocw3));
+ v3_chkpt_save_8(ctx, "MASTER_STATE", &(pic->master_state));
+ v3_chkpt_save_8(ctx, "SLAVE_STATE", &(pic->slave_state));
+
+
return 0;
+
}
+static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct pic_internal * pic = (struct pic_internal *)private_data;
+
+
+ v3_chkpt_load_8(ctx, "MASTER_IRR", &(pic->master_irr));
+ v3_chkpt_load_8(ctx, "SLAVE_IRR", &(pic->slave_irr));
+
+ v3_chkpt_load_8(ctx, "MASTER_ISR", &(pic->master_isr));
+ v3_chkpt_load_8(ctx, "SLAVE_ISR", &(pic->slave_isr));
+
+ v3_chkpt_load_8(ctx, "MASTER_ELCR", &(pic->master_elcr));
+ v3_chkpt_load_8(ctx, "SLAVE_ELCR", &(pic->slave_elcr));
+ v3_chkpt_load_8(ctx, "MASTER_ELCR_MASK", &(pic->master_elcr_mask));
+ v3_chkpt_load_8(ctx, "SLAVE_ELCR_MASK", &(pic->slave_elcr_mask));
+ v3_chkpt_load_8(ctx, "MASTER_ICW1", &(pic->master_icw1));
+ v3_chkpt_load_8(ctx, "MASTER_ICW2", &(pic->master_icw2));
+ v3_chkpt_load_8(ctx, "MASTER_ICW3", &(pic->master_icw3));
+ v3_chkpt_load_8(ctx, "MASTER_ICW4", &(pic->master_icw4));
+ v3_chkpt_load_8(ctx, "SLAVE_ICW1", &(pic->slave_icw1));
+ v3_chkpt_load_8(ctx, "SLAVE_ICW2", &(pic->slave_icw2));
+ v3_chkpt_load_8(ctx, "SLAVE_ICW3", &(pic->slave_icw3));
+ v3_chkpt_load_8(ctx, "SLAVE_ICW4", &(pic->slave_icw4));
+ v3_chkpt_load_8(ctx, "MASTER_IMR", &(pic->master_imr));
+ v3_chkpt_load_8(ctx, "SLAVE_IMR", &(pic->slave_imr));
+ v3_chkpt_load_8(ctx, "MASTER_OCW2", &(pic->master_ocw2));
+ v3_chkpt_load_8(ctx, "MASTER_OCW3", &(pic->master_ocw3));
+ v3_chkpt_load_8(ctx, "SLAVE_OCW2", &(pic->slave_ocw2));
+ v3_chkpt_load_8(ctx, "SLAVE_OCW3", &(pic->slave_ocw3));
+
+ v3_chkpt_load_8(ctx, "MASTER_STATE", &(pic->master_state));
+ v3_chkpt_load_8(ctx, "SLAVE_STATE", &(pic->slave_state));
+
+ return 0;
+}
+
+#endif
+
static struct v3_device_ops dev_ops = {
- .free = pic_free,
- .reset = NULL,
- .start = NULL,
- .stop = NULL,
+ .free = (int (*)(void *))pic_free,
+#ifdef V3_CONFIG_CHECKPOINT
+ .save = pic_save,
+ .load = pic_load
+#endif
};
-#include <palacios/vm_guest.h>
+
static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
struct pic_internal * state = NULL;
- state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
- char * name = v3_cfg_val(cfg, "name");
+ char * dev_id = v3_cfg_val(cfg, "ID");
+ int ret = 0;
// PIC is only usable in non-multicore environments
// just hardcode the core context
struct guest_info * core = &(vm->cores[0]);
+
+ state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
V3_ASSERT(state != NULL);
- struct vm_device * dev = v3_allocate_device(name, &dev_ops, state);
+ struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state);
- if (v3_attach_device(vm, dev) == -1) {
- PrintError("Could not attach device %s\n", name);
+ if (dev == NULL) {
+ PrintError("Could not add device %s\n", dev_id);
+ V3_Free(state);
return -1;
}
+ state->core = core;
- v3_register_intr_controller(core, &intr_ops, state);
- v3_register_intr_router(vm, &router_ops, state);
+ state->controller_handle = v3_register_intr_controller(core, &intr_ops, state);
+ state->router_handle = v3_register_intr_router(vm, &router_ops, state);
state->master_irr = 0;
state->master_isr = 0;
state->slave_state = ICW1;
- v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
- v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
- v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
- v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
+ ret |= v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
+ ret |= v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
+ ret |= v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
+ ret |= v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
+
+ ret |= v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
+ ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
- v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
- v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
+ if (ret != 0) {
+ PrintError("Error hooking io ports\n");
+ v3_remove_device(dev);
+ return -1;
+ }
return 0;
}
