#include <palacios/vmm_types.h>
#include <palacios/vmm.h>
#include <palacios/vmm_dev_mgr.h>
+#include <palacios/vm_guest.h>
-#ifndef CONFIG_DEBUG_PIC
+#ifndef V3_CONFIG_DEBUG_PIC
#undef PrintDebug
#define PrintDebug(fmt, args...)
#endif
pic_state_t master_state;
pic_state_t slave_state;
+
+ struct guest_info * core;
+
+
+ void * router_handle;
+ void * controller_handle;
};
}
-static int pic_raise_intr(void * private_data, int irq) {
+static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, int irq) {
struct pic_internal * state = (struct pic_internal*)private_data;
if (irq == 2) {
return -1;
}
+#ifdef V3_CONFIG_MULTITHREAD_OS
+ v3_interrupt_cpu(vm, 0, 0);
+#endif
+
return 0;
}
-static int pic_lower_intr(void *private_data, int irq) {
-
- struct pic_internal *state = (struct pic_internal*)private_data;
+static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, int irq) {
+ struct pic_internal * state = (struct pic_internal*)private_data;
PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq);
if (irq <= 7) {
-static int pic_intr_pending(void * private_data) {
+static int pic_intr_pending(struct guest_info * info, void * private_data) {
struct pic_internal * state = (struct pic_internal*)private_data;
if ((state->master_irr & ~(state->master_imr)) ||
return 0;
}
-static int pic_get_intr_number(void * private_data) {
+static int pic_get_intr_number(struct guest_info * info, void * private_data) {
struct pic_internal * state = (struct pic_internal *)private_data;
int i = 0;
int irq = -1;
for (i = 0; i < 16; i++) {
if (i <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
+ if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
//state->master_isr |= (0x1 << i);
// reset the irr
//state->master_irr &= ~(0x1 << i);
break;
}
} else {
- if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
+ if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
//state->slave_isr |= (0x1 << (i - 8));
//state->slave_irr &= ~(0x1 << (i - 8));
PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
- irq= (i - 8) + state->slave_icw2;
+ irq = (i - 8) + state->slave_icw2;
break;
}
}
}
+#if 1
if ((i == 15) || (i == 6)) {
DumpPICState(state);
}
+#endif
if (i == 16) {
return -1;
} else {
+ PrintDebug("8259 PIC: get num is returning %d\n",irq);
return irq;
}
}
/* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
-static int pic_begin_irq(void * private_data, int irq) {
+static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) {
struct pic_internal * state = (struct pic_internal*)private_data;
-
+
if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
- irq &= 0x7;
+ irq &= 0x7;
} else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
- irq &= 0x7;
- irq += 8;
+ irq &= 0x7;
+ irq += 8;
} else {
- // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
- return -1;
+ // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
+ return -1;
}
-
+
if (irq <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
- state->master_isr |= (0x1 << irq);
+ // This should always be true: See pic_get_intr_number
+ if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) {
+ state->master_isr |= (0x1 << irq);
- if (!(state->master_elcr & (0x1 << irq))) {
- state->master_irr &= ~(0x1 << irq);
- }
- }
- } else {
- state->slave_isr |= (0x1 << (irq - 8));
+ if (!(state->master_elcr & (0x1 << irq))) {
+ state->master_irr &= ~(0x1 << irq);
+ }
+ } else {
+ PrintDebug("8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n",irq);
+ }
- if (!(state->slave_elcr & (0x1 << irq))) {
- state->slave_irr &= ~(0x1 << (irq - 8));
+ } else {
+ // This should always be true: See pic_get_intr_number
+ if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) {
+ state->slave_isr |= (0x1 << (irq - 8));
+
+ if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
+ state->slave_irr &= ~(0x1 << (irq - 8));
+ }
+ } else {
+ PrintDebug("8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n",irq);
}
+
}
return 0;
static struct intr_ctrl_ops intr_ops = {
.intr_pending = pic_intr_pending,
.get_intr_number = pic_get_intr_number,
- .raise_intr = pic_raise_intr,
- .begin_irq = pic_begin_irq,
- .lower_intr = pic_lower_intr,
-
+ .begin_irq = pic_begin_irq
};
+static struct intr_router_ops router_ops = {
+ .raise_intr = pic_raise_intr,
+ .lower_intr = pic_lower_intr
+};
-
-static int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
return 1;
}
-static int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
}
-static int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
return 1;
}
-static int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
}
-static int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
uchar_t cw = *(uchar_t *)src;
PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
if (length != 1) {
- PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
- return -1;
+ PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
+ return -1;
}
-
+
+ v3_clear_pending_intr(core);
+
if (IS_ICW1(cw)) {
- PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
-
- state->master_icw1 = cw;
- state->master_state = ICW2;
+ PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
- } else if (state->master_state == READY) {
- if (IS_OCW2(cw)) {
- // handle the EOI here
- struct ocw2 * cw2 = (struct ocw2*)&cw;
+ state->master_icw1 = cw;
+ state->master_state = ICW2;
- PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
-
- if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
- // specific EOI;
- state->master_isr &= ~(0x01 << cw2->level);
- } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
- int i;
- // Non-specific EOI
- PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
- for (i = 0; i < 8; i++) {
- if (state->master_isr & (0x01 << i)) {
- state->master_isr &= ~(0x01 << i);
- break;
- }
- }
- PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
+ } else if (state->master_state == READY) {
+ if (IS_OCW2(cw)) {
+ // handle the EOI here
+ struct ocw2 * cw2 = (struct ocw2*)&cw;
+
+ PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
+
+ if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
+ // specific EOI;
+ state->master_isr &= ~(0x01 << cw2->level);
+ } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
+ int i;
+ // Non-specific EOI
+ PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
+ for (i = 0; i < 8; i++) {
+ if (state->master_isr & (0x01 << i)) {
+ state->master_isr &= ~(0x01 << i);
+ break;
+ }
+ }
+ PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
+ } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) {
+ PrintDebug("8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level);
+ } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) {
+ PrintDebug("8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level);
} else {
- PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
- return -1;
- }
-
- state->master_ocw2 = cw;
- } else if (IS_OCW3(cw)) {
- PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
- state->master_ocw3 = cw;
- } else {
- PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
- PrintError("8259 PIC: CW=%x\n", cw);
- return -1;
- }
+ PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
+ return -1;
+ }
+
+ state->master_ocw2 = cw;
+ } else if (IS_OCW3(cw)) {
+ PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
+ state->master_ocw3 = cw;
+ } else {
+ PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
+ PrintError("8259 PIC: CW=%x\n", cw);
+ return -1;
+ }
} else {
- PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
- PrintError("8259 PIC: CW=%x\n", cw);
- return -1;
+ PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
+ PrintError("8259 PIC: CW=%x\n", cw);
+ return -1;
}
return 1;
}
-static int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
uchar_t cw = *(uchar_t *)src;
PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
-
+
if (length != 1) {
- PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
- return -1;
+ PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
+ return -1;
}
-
+
+ v3_clear_pending_intr(core);
+
if (state->master_state == ICW2) {
- struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+
+ PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
+ state->master_icw2 = cw;
+
+
+
+ if (cw1->sngl == 0) {
+ state->master_state = ICW3;
+ } else if (cw1->ic4 == 1) {
+ state->master_state = ICW4;
+ } else {
+ state->master_state = READY;
+ }
- PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
- state->master_icw2 = cw;
- if (cw1->sngl == 0) {
- state->master_state = ICW3;
- } else if (cw1->ic4 == 1) {
- state->master_state = ICW4;
- } else {
- state->master_state = READY;
- }
} else if (state->master_state == ICW3) {
- struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
- PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
+ PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
- state->master_icw3 = cw;
+ state->master_icw3 = cw;
- if (cw1->ic4 == 1) {
- state->master_state = ICW4;
- } else {
- state->master_state = READY;
- }
+ if (cw1->ic4 == 1) {
+ state->master_state = ICW4;
+ } else {
+ state->master_state = READY;
+ }
} else if (state->master_state == ICW4) {
- PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
- state->master_icw4 = cw;
- state->master_state = READY;
- } else if (state->master_state == READY) {
- PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
- state->master_imr = cw;
+ PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
+ state->master_icw4 = cw;
+ state->master_state = READY;
+ } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
+ PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
+ state->master_imr = cw;
} else {
- // error
- PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
- return -1;
+ // error
+ PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n",
+ state->master_state);
+ return -1;
}
return 1;
}
-static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
uchar_t cw = *(uchar_t *)src;
PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
return -1;
}
+ v3_clear_pending_intr(core);
+
if (IS_ICW1(cw)) {
PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
state->slave_icw1 = cw;
return 1;
}
-static int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
uchar_t cw = *(uchar_t *)src;
PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
if (length != 1) {
- PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
- return -1;
+ PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
+ return -1;
}
+ v3_clear_pending_intr(core);
+
+
if (state->slave_state == ICW2) {
- struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
- PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
+ PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
- state->slave_icw2 = cw;
+ state->slave_icw2 = cw;
- if (cw1->sngl == 0) {
- state->slave_state = ICW3;
- } else if (cw1->ic4 == 1) {
- state->slave_state = ICW4;
- } else {
- state->slave_state = READY;
- }
+ if (cw1->sngl == 0) {
+ state->slave_state = ICW3;
+ } else if (cw1->ic4 == 1) {
+ state->slave_state = ICW4;
+ } else {
+ state->slave_state = READY;
+ }
} else if (state->slave_state == ICW3) {
- struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
- PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
+ PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
- state->slave_icw3 = cw;
+ state->slave_icw3 = cw;
- if (cw1->ic4 == 1) {
- state->slave_state = ICW4;
- } else {
- state->slave_state = READY;
- }
+ if (cw1->ic4 == 1) {
+ state->slave_state = ICW4;
+ } else {
+ state->slave_state = READY;
+ }
} else if (state->slave_state == ICW4) {
- PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
- state->slave_icw4 = cw;
- state->slave_state = READY;
- } else if (state->slave_state == READY) {
- PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
- state->slave_imr = cw;
+ PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
+ state->slave_icw4 = cw;
+ state->slave_state = READY;
+ } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
+ PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
+ state->slave_imr = cw;
} else {
- PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
- return -1;
+ PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
+ return -1;
}
return 1;
-static int read_elcr_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("ELCR read of invalid length %d\n", length);
}
-static int write_elcr_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
- struct pic_internal * state = (struct pic_internal*)dev->private_data;
+static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
+ struct pic_internal * state = (struct pic_internal *)priv_data;
if (length != 1) {
PrintError("ELCR read of invalid length %d\n", length);
+static int pic_free(struct pic_internal * state) {
+ struct guest_info * core = state->core;
+
+ v3_remove_intr_controller(core, state->controller_handle);
+ v3_remove_intr_router(core->vm_info, state->router_handle);
+
+ V3_Free(state);
+ return 0;
+}
+#ifdef V3_CONFIG_CHECKPOINT
+static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct pic_internal * pic = (struct pic_internal *)private_data;
+ V3_CHKPT_STD_SAVE(ctx, pic->master_irr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_irr);
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_isr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_isr);
-static int pic_free(struct vm_device * dev) {
- v3_dev_unhook_io(dev, MASTER_PORT1);
- v3_dev_unhook_io(dev, MASTER_PORT2);
- v3_dev_unhook_io(dev, SLAVE_PORT1);
- v3_dev_unhook_io(dev, SLAVE_PORT2);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_elcr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_elcr);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_elcr_mask);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_elcr_mask);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw1);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw3);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw4);
+
+
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw1);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw3);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw4);
+
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_imr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_imr);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_ocw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_ocw3);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_ocw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_ocw3);
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_state);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_state);
+
+
return 0;
+
}
+static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct pic_internal * pic = (struct pic_internal *)private_data;
+
+ V3_CHKPT_STD_LOAD(ctx, pic->master_irr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_irr);
+
+ V3_CHKPT_STD_LOAD(ctx, pic->master_isr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_isr);
+
+ V3_CHKPT_STD_LOAD(ctx, pic->master_elcr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_elcr);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_elcr_mask);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_elcr_mask);
+
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw1);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw4);
+
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw1);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw4);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_imr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_imr);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_ocw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_ocw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_ocw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_ocw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_state);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_state);
+
+ return 0;
+}
+
+#endif
static struct v3_device_ops dev_ops = {
- .free = pic_free,
- .reset = NULL,
- .start = NULL,
- .stop = NULL,
+ .free = (int (*)(void *))pic_free,
+#ifdef V3_CONFIG_CHECKPOINT
+ .save = pic_save,
+ .load = pic_load
+#endif
};
-static int pic_init(struct guest_info * vm, void * cfg_data) {
+
+
+static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
struct pic_internal * state = NULL;
+ char * dev_id = v3_cfg_val(cfg, "ID");
+ int ret = 0;
+
+ // PIC is only usable in non-multicore environments
+ // just hardcode the core context
+ struct guest_info * core = &(vm->cores[0]);
+
state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
+
V3_ASSERT(state != NULL);
- struct vm_device * dev = v3_allocate_device("8259A", &dev_ops, state);
+ struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state);
- if (v3_attach_device(vm, dev) == -1) {
- PrintError("Could not attach device %s\n", "8259A");
+ if (dev == NULL) {
+ PrintError("Could not add device %s\n", dev_id);
+ V3_Free(state);
return -1;
}
+ state->core = core;
- v3_register_intr_controller(vm, &intr_ops, state);
+ state->controller_handle = v3_register_intr_controller(core, &intr_ops, state);
+ state->router_handle = v3_register_intr_router(vm, &router_ops, state);
state->master_irr = 0;
state->master_isr = 0;
state->slave_state = ICW1;
- v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
- v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
- v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
- v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
+ ret |= v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
+ ret |= v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
+ ret |= v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
+ ret |= v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
- v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
- v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
+ ret |= v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
+ ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
+
+ if (ret != 0) {
+ PrintError("Error hooking io ports\n");
+ v3_remove_device(dev);
+ return -1;
+ }
return 0;
}
