-#ifndef __VMM_PAGING_H
-#define __VMM_PAGING_H
+/*
+ * This file is part of the Palacios Virtual Machine Monitor developed
+ * by the V3VEE Project with funding from the United States National
+ * Science Foundation and the Department of Energy.
+ *
+ * The V3VEE Project is a joint project between Northwestern University
+ * and the University of New Mexico. You can find out more at
+ * http://www.v3vee.org
+ *
+ * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
+ * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
+ * All rights reserved.
+ *
+ * Author: Jack Lange <jarusl@cs.northwestern.edu>
+ *
+ * This is free software. You are permitted to use,
+ * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
+ */
-#include <palacios/vmm_types.h>
+#ifndef __VMM_PAGING_H
+#define __VMM_PAGING_H
+#ifdef __V3VEE__
-#include <palacios/vmm_mem.h>
+#include <palacios/vmm_types.h>
#include <palacios/vmm_util.h>
/*
switch is done by the hardware. On Intel VT, the switch is done
by the hardware as well, but we are responsible for manually updating
the host state in the vmcs before entering the guest.
-
-
*/
#define MAX_PDPE64_ENTRIES 512
#define MAX_PML4E64_ENTRIES 512
+
+/* Converts an address into a page table index */
#define PDE32_INDEX(x) ((((uint_t)x) >> 22) & 0x3ff)
#define PTE32_INDEX(x) ((((uint_t)x) >> 12) & 0x3ff)
+/* Gets the base address needed for a Page Table entry */
+#define PD32_BASE_ADDR(x) (((uint_t)x) >> 12)
+#define PT32_BASE_ADDR(x) (((uint_t)x) >> 12)
+#define PD32_4MB_BASE_ADDR(x) (((uint_t)x) >> 22)
-#define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
+#define PT32_PAGE_ADDR(x) (((uint_t)x) & 0xfffff000)
+#define PT32_PAGE_OFFSET(x) (((uint_t)x) & 0xfff)
+#define PT32_PAGE_POWER 12
-#ifndef PAGE_ADDR
-#define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
-#endif
-#define PAGE_OFFSET(x) ((((uint_t)x) & 0xfff))
+#define PD32_4MB_PAGE_ADDR(x) (((uint_t)x) & 0xffc00000)
+#define PD32_4MB_PAGE_OFFSET(x) (((uint_t)x) & 0x003fffff)
+#define PAGE_SIZE_4MB (4096 * 1024)
+/* The following should be phased out */
+#define PAGE_OFFSET(x) ((((uint_t)x) & 0xfff))
+#define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
+#define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
#define PAGE_POWER 12
+#define PAGE_SIZE 4096
+/* ** */
+
+
+
#define CR3_TO_PDE32(cr3) (((ulong_t)cr3) & 0xfffff000)
#define CR3_TO_PDPTRE(cr3) (((ulong_t)cr3) & 0xffffffe0)
-#define CR3_TO_PML4E64(cr3) (((ullong_t)cr3) & 0x000ffffffffff000)
+#define CR3_TO_PML4E64(cr3) (((ullong_t)cr3) & 0x000ffffffffff000LL)
+
+
+
-#define VM_WRITE 1
-#define VM_USER 2
-#define VM_NOCACHE 8
-#define VM_READ 0
-#define VM_EXEC 0
+/* Accessor functions for the page table structures */
+#define PDE32_T_ADDR(x) (((x).pt_base_addr) << 12)
+#define PTE32_T_ADDR(x) (((x).page_base_addr) << 12)
+#define PDE32_4MB_T_ADDR(x) (((x).page_base_addr) << 22)
+/* Page Table Flag Values */
+#define PT32_HOOK 0x1
+#define PT32_GUEST_PT 0x2
+
+
+#endif
/* PDE 32 bit PAGE STRUCTURES */
-typedef enum {NOT_PRESENT, PTE32, LARGE_PAGE} pde32_entry_type_t;
+typedef enum {PDE32_ENTRY_NOT_PRESENT, PDE32_ENTRY_PTE32, PDE32_ENTRY_LARGE_PAGE} pde32_entry_type_t;
+typedef enum {PT_ACCESS_OK, PT_ENTRY_NOT_PRESENT, PT_WRITE_ERROR, PT_USER_ERROR} pt_access_status_t;
typedef struct pde32 {
uint_t present : 1;
- uint_t flags : 4;
+ uint_t writable : 1;
+ uint_t user_page : 1;
+ uint_t write_through : 1;
+ uint_t cache_disable : 1;
uint_t accessed : 1;
uint_t reserved : 1;
- uint_t large_pages : 1;
+ uint_t large_page : 1;
uint_t global_page : 1;
uint_t vmm_info : 3;
uint_t pt_base_addr : 20;
} pde32_t;
+typedef struct pde32_4MB {
+ uint_t present : 1;
+ uint_t writable : 1;
+ uint_t user_page : 1;
+ uint_t write_through : 1;
+ uint_t cache_disable : 1;
+ uint_t accessed : 1;
+ uint_t dirty : 1;
+ uint_t one : 1;
+ uint_t global_page : 1;
+ uint_t vmm_info : 3;
+ uint_t pat : 1;
+ uint_t rsvd : 9;
+ uint_t page_base_addr : 10;
+
+} pde32_4MB_t;
+
typedef struct pte32 {
uint_t present : 1;
- uint_t flags : 4;
+ uint_t writable : 1;
+ uint_t user_page : 1;
+ uint_t write_through : 1;
+ uint_t cache_disable : 1;
uint_t accessed : 1;
uint_t dirty : 1;
uint_t pte_attr : 1;
/* *************** */
+typedef struct pf_error_code {
+ uint_t present : 1; // if 0, fault due to page not present
+ uint_t write : 1; // if 1, faulting access was a write
+ uint_t user : 1; // if 1, faulting access was in user mode
+ uint_t rsvd_access : 1; // if 1, fault from reading a 1 from a reserved field (?)
+ uint_t ifetch : 1; // if 1, faulting access was an instr fetch (only with NX)
+ uint_t rsvd : 27;
+} pf_error_t;
typedef enum { PDE32 } paging_mode_t;
void delete_page_tables_pde32(pde32_t * pde);
-pde32_entry_type_t pde32_lookup(pde32_t * pde, addr_t addr, addr_t * entry);
+pde32_entry_type_t pde32_lookup(pde32_t * pd, addr_t addr, addr_t * entry);
int pte32_lookup(pte32_t * pte, addr_t addr, addr_t * entry);
+// This assumes that the page table resides in the host address space
+// IE. IT DOES NO VM ADDR TRANSLATION
+int pt32_lookup(pde32_t * pd, addr_t vaddr, addr_t * paddr);
+
+
+
+pt_access_status_t can_access_pde32(pde32_t * pde, addr_t addr, pf_error_t access_type);
+pt_access_status_t can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
+
+
+
struct guest_info;
void PrintDebugPageTables(pde32_t * pde);
+#ifdef __V3VEE__
+
+
+void PrintPT32(addr_t starting_address, pte32_t * pte);
+void PrintPD32(pde32_t * pde);
+void PrintPTE32(addr_t virtual_address, pte32_t * pte);
+void PrintPDE32(addr_t virtual_address, pde32_t * pde);
+
+#endif // !__V3VEE__
+
#endif
