2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2011, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2011, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmx.h>
22 #include <palacios/vmm.h>
23 #include <palacios/vmx_handler.h>
24 #include <palacios/vmcs.h>
25 #include <palacios/vmx_lowlevel.h>
26 #include <palacios/vmm_lowlevel.h>
27 #include <palacios/vmm_ctrl_regs.h>
28 #include <palacios/vmm_config.h>
29 #include <palacios/vmm_time.h>
30 #include <palacios/vm_guest_mem.h>
31 #include <palacios/vmm_direct_paging.h>
32 #include <palacios/vmx_io.h>
33 #include <palacios/vmx_msr.h>
34 #include <palacios/vmm_decoder.h>
35 #include <palacios/vmm_barrier.h>
36 #include <palacios/vmm_timeout.h>
37 #include <palacios/vmm_debug.h>
39 #ifdef V3_CONFIG_CHECKPOINT
40 #include <palacios/vmm_checkpoint.h>
43 #include <palacios/vmx_ept.h>
44 #include <palacios/vmx_assist.h>
45 #include <palacios/vmx_hw_info.h>
47 #ifndef V3_CONFIG_DEBUG_VMX
49 #define PrintDebug(fmt, args...)
53 /* These fields contain the hardware feature sets supported by the local CPU */
54 static struct vmx_hw_info hw_info;
56 extern v3_cpu_arch_t v3_mach_type;
58 static addr_t host_vmcs_ptrs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
60 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
61 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
63 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
66 ret = vmcs_write(field, val);
68 if (ret != VMX_SUCCESS) {
69 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
79 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
82 ret = vmcs_read(field, val);
84 if (ret != VMX_SUCCESS) {
85 PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
94 static addr_t allocate_vmcs() {
96 struct vmcs_data * vmcs_page = NULL;
98 PrintDebug("Allocating page\n");
100 temp = V3_AllocPages(1);
102 PrintError("Cannot allocate VMCS\n");
105 vmcs_page = (struct vmcs_data *)V3_VAddr(temp);
106 memset(vmcs_page, 0, 4096);
108 vmcs_page->revision = hw_info.basic_info.revision;
109 PrintDebug("VMX Revision: 0x%x\n", vmcs_page->revision);
111 return (addr_t)V3_PAddr((void *)vmcs_page);
116 static int debug_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * src, void * priv_data) {
117 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
118 V3_Print("\n\nEFER READ (val = %p)\n", (void *)efer->value);
120 v3_print_guest_state(core);
124 src->value = efer->value;
128 static int debug_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
129 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
130 V3_Print("\n\nEFER WRITE (old_val = %p) (new_val = %p)\n", (void *)efer->value, (void *)src.value);
132 v3_print_guest_state(core);
135 efer->value = src.value;
142 static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) {
145 /* Get Available features */
146 struct vmx_pin_ctrls avail_pin_ctrls;
147 avail_pin_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.pin_ctrls));
151 // disable global interrupts for vm state initialization
154 PrintDebug("Loading VMCS\n");
155 vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
156 vmx_state->state = VMX_UNLAUNCHED;
158 if (vmx_ret != VMX_SUCCESS) {
159 PrintError("VMPTRLD failed\n");
164 /*** Setup default state from HW ***/
166 vmx_state->pin_ctrls.value = hw_info.pin_ctrls.def_val;
167 vmx_state->pri_proc_ctrls.value = hw_info.proc_ctrls.def_val;
168 vmx_state->exit_ctrls.value = hw_info.exit_ctrls.def_val;
169 vmx_state->entry_ctrls.value = hw_info.entry_ctrls.def_val;
170 vmx_state->sec_proc_ctrls.value = hw_info.sec_proc_ctrls.def_val;
172 /* Print Control MSRs */
173 V3_Print("CR0 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr0.req_val, (void *)(addr_t)hw_info.cr0.req_mask);
174 V3_Print("CR4 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr4.req_val, (void *)(addr_t)hw_info.cr4.req_mask);
178 /******* Setup Host State **********/
180 /* Cache GDTR, IDTR, and TR in host struct */
183 /********** Setup VMX Control Fields ***********/
185 /* Add external interrupts, NMI exiting, and virtual NMI */
186 vmx_state->pin_ctrls.nmi_exit = 1;
187 vmx_state->pin_ctrls.virt_nmi = 1;
188 vmx_state->pin_ctrls.ext_int_exit = 1;
192 /* We enable the preemption timer by default to measure accurate guest time */
193 if (avail_pin_ctrls.active_preempt_timer) {
194 V3_Print("VMX Preemption Timer is available\n");
195 vmx_state->pin_ctrls.active_preempt_timer = 1;
196 vmx_state->exit_ctrls.save_preempt_timer = 1;
199 // we want it to use this when halting
200 vmx_state->pri_proc_ctrls.hlt_exit = 1;
202 // cpuid tells it that it does not have these instructions
203 vmx_state->pri_proc_ctrls.monitor_exit = 1;
204 vmx_state->pri_proc_ctrls.mwait_exit = 1;
206 // we don't need to handle a pause, although this is where
207 // we could pull out of a spin lock acquire or schedule to find its partner
208 vmx_state->pri_proc_ctrls.pause_exit = 0;
210 vmx_state->pri_proc_ctrls.tsc_offset = 1;
211 #ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC
212 vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
216 vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
217 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(core->vm_info->io_map.arch_data));
218 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
219 (addr_t)V3_PAddr(core->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
222 vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
223 vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data));
228 // Ensure host runs in 64-bit mode at each VM EXIT
229 vmx_state->exit_ctrls.host_64_on = 1;
234 // Restore host's EFER register on each VM EXIT
235 vmx_state->exit_ctrls.ld_efer = 1;
237 // Save/restore guest's EFER register to/from VMCS on VM EXIT/ENTRY
238 vmx_state->exit_ctrls.save_efer = 1;
239 vmx_state->entry_ctrls.ld_efer = 1;
241 vmx_state->exit_ctrls.save_pat = 1;
242 vmx_state->exit_ctrls.ld_pat = 1;
243 vmx_state->entry_ctrls.ld_pat = 1;
245 /* Temporary GPF trap */
246 // vmx_state->excp_bmap.gp = 1;
248 // Setup Guests initial PAT field
249 vmx_ret |= check_vmcs_write(VMCS_GUEST_PAT, 0x0007040600070406LL);
251 // Capture CR8 mods so that we can keep the apic_tpr correct
252 vmx_state->pri_proc_ctrls.cr8_ld_exit = 1;
253 vmx_state->pri_proc_ctrls.cr8_str_exit = 1;
257 if (core->shdw_pg_mode == SHADOW_PAGING) {
258 PrintDebug("Creating initial shadow page table\n");
260 if (v3_init_passthrough_pts(core) == -1) {
261 PrintError("Could not initialize passthrough page tables\n");
265 #define CR0_PE 0x00000001
266 #define CR0_PG 0x80000000
267 #define CR0_WP 0x00010000 // To ensure mem hooks work
268 #define CR0_NE 0x00000020
269 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE));
272 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
273 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
275 core->ctrl_regs.cr3 = core->direct_map_pt;
277 // vmx_state->pinbased_ctrls |= NMI_EXIT;
280 vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
281 vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
283 vmx_state->pri_proc_ctrls.invlpg_exit = 1;
285 /* Add page fault exits */
286 vmx_state->excp_bmap.pf = 1;
289 v3_vmxassist_init(core, vmx_state);
291 // Hook all accesses to EFER register
292 v3_hook_msr(core->vm_info, EFER_MSR,
293 &v3_handle_efer_read,
294 &v3_handle_efer_write,
297 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
298 (v3_mach_type == V3_VMX_EPT_CPU)) {
300 #define CR0_PE 0x00000001
301 #define CR0_PG 0x80000000
302 #define CR0_WP 0x00010000 // To ensure mem hooks work
303 #define CR0_NE 0x00000020
304 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE));
306 // vmx_state->pinbased_ctrls |= NMI_EXIT;
308 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
309 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
311 /* Disable CR exits */
312 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
313 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
315 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
317 /* Add page fault exits */
318 // vmx_state->excp_bmap.pf = 1; // This should never happen..., enabled to catch bugs
321 v3_vmxassist_init(core, vmx_state);
324 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
325 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
329 if (v3_init_ept(core, &hw_info) == -1) {
330 PrintError("Error initializing EPT\n");
334 // Hook all accesses to EFER register
335 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
337 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
338 (v3_mach_type == V3_VMX_EPT_UG_CPU)) {
340 // For now we will assume that unrestricted guest mode is assured w/ EPT
343 core->vm_regs.rsp = 0x00;
345 core->vm_regs.rdx = 0x00000f00;
346 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
347 core->ctrl_regs.cr0 = 0x60010030;
348 core->ctrl_regs.cr4 = 0x00002010; // Enable VMX and PSE flag
351 core->segments.cs.selector = 0xf000;
352 core->segments.cs.limit = 0xffff;
353 core->segments.cs.base = 0x0000000f0000LL;
355 // (raw attributes = 0xf3)
356 core->segments.cs.type = 0xb;
357 core->segments.cs.system = 0x1;
358 core->segments.cs.dpl = 0x0;
359 core->segments.cs.present = 1;
363 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
364 &(core->segments.es), &(core->segments.fs),
365 &(core->segments.gs), NULL};
367 for ( i = 0; segregs[i] != NULL; i++) {
368 struct v3_segment * seg = segregs[i];
370 seg->selector = 0x0000;
371 // seg->base = seg->selector << 4;
372 seg->base = 0x00000000;
380 // seg->granularity = 1;
385 core->segments.gdtr.limit = 0x0000ffff;
386 core->segments.gdtr.base = 0x0000000000000000LL;
388 core->segments.idtr.limit = 0x0000ffff;
389 core->segments.idtr.base = 0x0000000000000000LL;
391 core->segments.ldtr.selector = 0x0000;
392 core->segments.ldtr.limit = 0x0000ffff;
393 core->segments.ldtr.base = 0x0000000000000000LL;
394 core->segments.ldtr.type = 0x2;
395 core->segments.ldtr.present = 1;
397 core->segments.tr.selector = 0x0000;
398 core->segments.tr.limit = 0x0000ffff;
399 core->segments.tr.base = 0x0000000000000000LL;
400 core->segments.tr.type = 0xb;
401 core->segments.tr.present = 1;
403 // core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
404 core->dbg_regs.dr7 = 0x0000000000000400LL;
407 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
408 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
409 vmx_state->sec_proc_ctrls.unrstrct_guest = 1; // enable unrestricted guest operation
412 /* Disable shadow paging stuff */
413 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
414 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
416 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
419 // Cause VM_EXIT whenever the CR4.VMXE bit is set
420 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
421 #define CR0_NE 0x00000020
422 #define CR0_CD 0x40000000
423 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, CR0_NE | CR0_CD);
424 ((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->ne = 1;
425 ((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->cd = 0;
427 if (v3_init_ept(core, &hw_info) == -1) {
428 PrintError("Error initializing EPT\n");
432 // Hook all accesses to EFER register
433 // v3_hook_msr(core->vm_info, EFER_MSR, &debug_efer_read, &debug_efer_write, core);
434 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
436 PrintError("Invalid Virtual paging mode (pg_mode=%d) (mach_type=%d)\n", core->shdw_pg_mode, v3_mach_type);
443 // Setup SYSCALL/SYSENTER MSRs in load/store area
445 // save STAR, LSTAR, FMASK, KERNEL_GS_BASE MSRs in MSR load/store area
448 struct vmcs_msr_save_area * msr_entries = NULL;
449 int max_msrs = (hw_info.misc_info.max_msr_cache_size + 1) * 4;
452 V3_Print("Setting up MSR load/store areas (max_msr_count=%d)\n", max_msrs);
455 PrintError("Max MSR cache size is too small (%d)\n", max_msrs);
459 vmx_state->msr_area_paddr = (addr_t)V3_AllocPages(1);
461 if (vmx_state->msr_area_paddr == (addr_t)NULL) {
462 PrintError("could not allocate msr load/store area\n");
466 msr_entries = (struct vmcs_msr_save_area *)V3_VAddr((void *)(vmx_state->msr_area_paddr));
467 vmx_state->msr_area = msr_entries; // cache in vmx_info
469 memset(msr_entries, 0, PAGE_SIZE);
471 msr_entries->guest_star.index = IA32_STAR_MSR;
472 msr_entries->guest_lstar.index = IA32_LSTAR_MSR;
473 msr_entries->guest_fmask.index = IA32_FMASK_MSR;
474 msr_entries->guest_kern_gs.index = IA32_KERN_GS_BASE_MSR;
476 msr_entries->host_star.index = IA32_STAR_MSR;
477 msr_entries->host_lstar.index = IA32_LSTAR_MSR;
478 msr_entries->host_fmask.index = IA32_FMASK_MSR;
479 msr_entries->host_kern_gs.index = IA32_KERN_GS_BASE_MSR;
481 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_CNT, 4);
482 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_CNT, 4);
483 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_CNT, 4);
485 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
486 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
487 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->host_msrs));
490 msr_ret |= v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
491 msr_ret |= v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
492 msr_ret |= v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
493 msr_ret |= v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
496 // IMPORTANT: These MSRs appear to be cached by the hardware....
497 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
498 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
499 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
501 msr_ret |= v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
502 msr_ret |= v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
504 msr_ret |= v3_hook_msr(core->vm_info, IA32_PAT_MSR, NULL, NULL, NULL);
506 // Not sure what to do about this... Does not appear to be an explicit hardware cache version...
507 msr_ret |= v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
510 PrintError("Error configuring MSR save/restore area\n");
517 /* Sanity check ctrl/reg fields against hw_defaults */
522 /*** Write all the info to the VMCS ***/
526 // IS THIS NECESSARY???
527 #define DEBUGCTL_MSR 0x1d9
528 struct v3_msr tmp_msr;
529 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
530 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
531 core->dbg_regs.dr7 = 0x400;
536 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
538 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL);
539 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
546 if (v3_update_vmcs_ctrl_fields(core)) {
547 PrintError("Could not write control fields!\n");
552 if (v3_update_vmcs_host_state(core)) {
553 PrintError("Could not write host state\n");
558 // reenable global interrupts for vm state initialization now
559 // that the vm state is initialized. If another VM kicks us off,
560 // it'll update our vmx state so that we know to reload ourself
567 static void __init_vmx_vmcs(void * arg) {
568 struct guest_info * core = arg;
569 struct vmx_data * vmx_state = NULL;
572 vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
575 PrintError("Unable to allocate in initializing vmx vmcs\n");
579 memset(vmx_state, 0, sizeof(struct vmx_data));
581 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
583 PrintDebug("Allocating VMCS\n");
584 vmx_state->vmcs_ptr_phys = allocate_vmcs();
586 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
588 core->vmm_data = vmx_state;
589 vmx_state->state = VMX_UNLAUNCHED;
591 PrintDebug("Initializing VMCS (addr=%p)\n", core->vmm_data);
593 // TODO: Fix vmcs fields so they're 32-bit
595 PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
596 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
598 if (vmx_ret != VMX_SUCCESS) {
599 PrintError("VMCLEAR failed\n");
603 if (core->vm_info->vm_class == V3_PC_VM) {
604 PrintDebug("Initializing VMCS\n");
605 if (init_vmcs_bios(core, vmx_state) == -1) {
606 PrintError("Error initializing VMCS to BIOS state\n");
610 PrintError("Invalid VM Class\n");
614 PrintDebug("Serializing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
615 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
617 core->core_run_state = CORE_STOPPED;
623 int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) {
624 extern v3_cpu_arch_t v3_cpu_types[];
626 if (v3_cpu_types[V3_Get_CPU()] == V3_INVALID_CPU) {
629 for (i = 0; i < V3_CONFIG_MAX_CPUS; i++) {
630 if (v3_cpu_types[i] != V3_INVALID_CPU) {
635 if (i == V3_CONFIG_MAX_CPUS) {
636 PrintError("Could not find VALID CPU for VMX guest initialization\n");
640 V3_Call_On_CPU(i, __init_vmx_vmcs, core);
643 __init_vmx_vmcs(core);
646 if (core->core_run_state != CORE_STOPPED) {
647 PrintError("Error initializing VMX Core\n");
655 int v3_deinit_vmx_vmcs(struct guest_info * core) {
656 struct vmx_data * vmx_state = core->vmm_data;
658 V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1);
659 V3_FreePages(V3_PAddr(vmx_state->msr_area), 1);
668 #ifdef V3_CONFIG_CHECKPOINT
670 * JRL: This is broken
672 int v3_vmx_save_core(struct guest_info * core, void * ctx){
673 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
675 // note that the vmcs pointer is an HPA, but we need an HVA
676 if (v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE_4KB,
677 V3_VAddr((void*) (vmx_info->vmcs_ptr_phys))) ==-1) {
678 PrintError("Could not save vmcs data for VMX\n");
685 int v3_vmx_load_core(struct guest_info * core, void * ctx){
686 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
687 struct cr0_32 * shadow_cr0;
688 addr_t vmcs_page_paddr; //HPA
690 vmcs_page_paddr = (addr_t) V3_AllocPages(1);
692 if (!vmcs_page_paddr) {
693 PrintError("Could not allocate space for a vmcs in VMX\n");
697 if (v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB,
698 V3_VAddr((void *)vmcs_page_paddr)) == -1) {
699 PrintError("Could not load vmcs data for VMX\n");
703 vmcs_clear(vmx_info->vmcs_ptr_phys);
705 // Probably need to delete the old one...
706 V3_FreePages((void*)(vmx_info->vmcs_ptr_phys),1);
708 vmcs_load(vmcs_page_paddr);
710 v3_vmx_save_vmcs(core);
712 shadow_cr0 = (struct cr0_32 *)&(core->ctrl_regs.cr0);
715 /* Get the CPU mode to set the guest_ia32e entry ctrl */
717 if (core->shdw_pg_mode == SHADOW_PAGING) {
718 if (v3_get_vm_mem_mode(core) == VIRTUAL_MEM) {
719 if (v3_activate_shadow_pt(core) == -1) {
720 PrintError("Failed to activate shadow page tables\n");
724 if (v3_activate_passthrough_pt(core) == -1) {
725 PrintError("Failed to activate passthrough page tables\n");
736 void v3_flush_vmx_vm_core(struct guest_info * core) {
737 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
738 vmcs_clear(vmx_info->vmcs_ptr_phys);
739 vmx_info->state = VMX_UNLAUNCHED;
744 static int update_irq_exit_state(struct guest_info * info) {
745 struct vmx_exit_idt_vec_info idt_vec_info;
747 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
749 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
750 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
751 V3_Print("Calling v3_injecting_intr\n");
753 info->intr_core_state.irq_started = 0;
754 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
760 static int update_irq_entry_state(struct guest_info * info) {
761 struct vmx_exit_idt_vec_info idt_vec_info;
762 struct vmcs_interrupt_state intr_core_state;
763 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
765 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
766 check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
768 /* Check for pending exceptions to inject */
769 if (v3_excp_pending(info)) {
770 struct vmx_entry_int_info int_info;
773 // In VMX, almost every exception is hardware
774 // Software exceptions are pretty much only for breakpoint or overflow
776 int_info.vector = v3_get_excp_number(info);
778 if (info->excp_state.excp_error_code_valid) {
779 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
780 int_info.error_code = 1;
782 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
783 V3_Print("Injecting exception %d with error code %x\n",
784 int_info.vector, info->excp_state.excp_error_code);
789 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
790 V3_Print("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
792 check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
794 v3_injecting_excp(info, int_info.vector);
796 } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
797 (intr_core_state.val == 0)) {
799 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
801 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
802 V3_Print("IRQ pending from previous injection\n");
805 // Copy the IDT vectoring info over to reinject the old interrupt
806 if (idt_vec_info.error_code == 1) {
807 uint32_t err_code = 0;
809 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
810 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
813 idt_vec_info.undef = 0;
814 check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
817 struct vmx_entry_int_info ent_int;
820 switch (v3_intr_pending(info)) {
821 case V3_EXTERNAL_IRQ: {
822 info->intr_core_state.irq_vector = v3_get_intr(info);
823 ent_int.vector = info->intr_core_state.irq_vector;
825 ent_int.error_code = 0;
828 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
829 V3_Print("Injecting Interrupt %d at exit %u(EIP=%p)\n",
830 info->intr_core_state.irq_vector,
831 (uint32_t)info->num_exits,
832 (void *)(addr_t)info->rip);
835 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
836 info->intr_core_state.irq_started = 1;
841 PrintDebug("Injecting NMI\n");
846 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
849 case V3_SOFTWARE_INTR:
850 PrintDebug("Injecting software interrupt\n");
854 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
858 // Not sure what to do here, Intel doesn't have virtual IRQs
859 // May be the same as external interrupts/IRQs
862 case V3_INVALID_INTR:
867 } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
868 // Enable INTR window exiting so we know when IF=1
871 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
873 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
874 V3_Print("Enabling Interrupt-Window exiting: %d\n", instr_len);
877 vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
878 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
887 static struct vmx_exit_info exit_log[10];
888 static uint64_t rip_log[10];
892 static void print_exit_log(struct guest_info * info) {
893 int cnt = info->num_exits % 10;
897 V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
899 for (i = 0; i < 10; i++) {
900 struct vmx_exit_info * tmp = &exit_log[cnt];
902 V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
903 V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
904 V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
905 V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
906 V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
907 V3_Print("\tguest_linear_addr= %p\n", (void *)(addr_t)tmp->guest_linear_addr);
908 V3_Print("\tRIP = %p\n", (void *)rip_log[cnt]);
922 v3_vmx_config_tsc_virtualization(struct guest_info * info) {
923 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
925 if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
926 if (!vmx_info->pri_proc_ctrls.rdtsc_exit) {
927 vmx_info->pri_proc_ctrls.rdtsc_exit = 1;
928 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
932 uint32_t tsc_offset_low, tsc_offset_high;
934 if (vmx_info->pri_proc_ctrls.rdtsc_exit) {
935 vmx_info->pri_proc_ctrls.rdtsc_exit = 0;
936 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
939 if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) {
942 tsc_offset = v3_tsc_host_offset(&info->time_state);
944 tsc_offset_high = (uint32_t)(( tsc_offset >> 32) & 0xffffffff);
945 tsc_offset_low = (uint32_t)(tsc_offset & 0xffffffff);
947 check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
948 check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
954 * CAUTION and DANGER!!!
956 * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
957 * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
958 * on its contents will cause things to break. The contents at the time of the exit WILL
959 * change before the exit handler is executed.
961 int v3_vmx_enter(struct guest_info * info) {
963 struct vmx_exit_info exit_info;
964 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
965 uint64_t guest_cycles = 0;
967 // Conditionally yield the CPU if the timeslice has expired
968 v3_yield_cond(info,-1);
970 // Update timer devices late after being in the VM so that as much
971 // of the time in the VM is accounted for as possible. Also do it before
972 // updating IRQ entry state so that any interrupts the timers raise get
973 // handled on the next VM entry.
974 v3_advance_time(info, NULL);
975 v3_update_timers(info);
977 // disable global interrupts for vm state transition
980 if (vmcs_store() != vmx_info->vmcs_ptr_phys) {
981 vmcs_clear(vmx_info->vmcs_ptr_phys);
982 vmcs_load(vmx_info->vmcs_ptr_phys);
983 vmx_info->state = VMX_UNLAUNCHED;
986 v3_vmx_restore_vmcs(info);
989 #ifdef V3_CONFIG_SYMCALL
990 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
991 update_irq_entry_state(info);
994 update_irq_entry_state(info);
999 vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
1000 vmcs_write(VMCS_GUEST_CR3, guest_cr3);
1004 // Perform last-minute time setup prior to entering the VM
1005 v3_vmx_config_tsc_virtualization(info);
1007 if (v3_update_vmcs_host_state(info)) {
1009 PrintError("Could not write host state\n");
1013 if (vmx_info->pin_ctrls.active_preempt_timer) {
1014 /* Preemption timer is active */
1015 uint32_t preempt_window = 0xffffffff;
1017 if (info->timeouts.timeout_active) {
1018 preempt_window = info->timeouts.next_timeout;
1021 check_vmcs_write(VMCS_PREEMPT_TIMER, preempt_window);
1026 uint64_t entry_tsc = 0;
1027 uint64_t exit_tsc = 0;
1029 if (vmx_info->state == VMX_UNLAUNCHED) {
1030 vmx_info->state = VMX_LAUNCHED;
1032 ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
1036 V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED);
1038 ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
1042 guest_cycles = exit_tsc - entry_tsc;
1045 // PrintDebug("VMX Exit: ret=%d\n", ret);
1047 if (ret != VMX_SUCCESS) {
1049 vmcs_read(VMCS_INSTR_ERR, &error);
1053 PrintError("VMENTRY Error: %d (launch_ret = %d)\n", error, ret);
1060 /* If we have the preemption time, then use it to get more accurate guest time */
1061 if (vmx_info->pin_ctrls.active_preempt_timer) {
1062 uint32_t cycles_left = 0;
1063 check_vmcs_read(VMCS_PREEMPT_TIMER, &(cycles_left));
1065 if (info->timeouts.timeout_active) {
1066 guest_cycles = info->timeouts.next_timeout - cycles_left;
1068 guest_cycles = 0xffffffff - cycles_left;
1072 // Immediate exit from VM time bookkeeping
1073 v3_advance_time(info, &guest_cycles);
1075 /* Update guest state */
1076 v3_vmx_save_vmcs(info);
1078 // info->cpl = info->segments.cs.selector & 0x3;
1080 info->mem_mode = v3_get_vm_mem_mode(info);
1081 info->cpu_mode = v3_get_vm_cpu_mode(info);
1085 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
1086 check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
1087 check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
1088 check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
1089 check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
1090 check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
1091 check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
1093 if (info->shdw_pg_mode == NESTED_PAGING) {
1094 check_vmcs_read(VMCS_GUEST_PHYS_ADDR, &(exit_info.ept_fault_addr));
1097 //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
1099 exit_log[info->num_exits % 10] = exit_info;
1100 rip_log[info->num_exits % 10] = get_addr_linear(info, info->rip, &(info->segments.cs));
1102 #ifdef V3_CONFIG_SYMCALL
1103 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
1104 update_irq_exit_state(info);
1107 update_irq_exit_state(info);
1110 if (exit_info.exit_reason == VMX_EXIT_INTR_WINDOW) {
1111 // This is a special case whose only job is to inject an interrupt
1112 vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value));
1113 vmx_info->pri_proc_ctrls.int_wndw_exit = 0;
1114 vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
1116 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
1117 V3_Print("Interrupts available again! (RIP=%llx)\n", info->rip);
1122 // Lastly we check for an NMI exit, and reinject if so
1124 struct vmx_basic_exit_info * basic_info = (struct vmx_basic_exit_info *)&(exit_info.exit_reason);
1126 if (basic_info->reason == VMX_EXIT_INFO_EXCEPTION_OR_NMI) {
1127 if ((uint8_t)exit_info.int_info == 2) {
1133 // reenable global interrupts after vm exit
1136 // Conditionally yield the CPU if the timeslice has expired
1137 v3_yield_cond(info,-1);
1138 v3_advance_time(info, NULL);
1139 v3_update_timers(info);
1141 if (v3_handle_vmx_exit(info, &exit_info) == -1) {
1142 PrintError("Error in VMX exit handler (Exit reason=%x)\n", exit_info.exit_reason);
1146 if (info->timeouts.timeout_active) {
1147 /* Check to see if any timeouts have expired */
1148 v3_handle_timeouts(info, guest_cycles);
1155 int v3_start_vmx_guest(struct guest_info * info) {
1157 PrintDebug("Starting VMX core %u\n", info->vcpu_id);
1159 if (info->vcpu_id == 0) {
1160 info->core_run_state = CORE_RUNNING;
1163 PrintDebug("VMX core %u: Waiting for core initialization\n", info->vcpu_id);
1165 while (info->core_run_state == CORE_STOPPED) {
1167 if (info->vm_info->run_state == VM_STOPPED) {
1168 // The VM was stopped before this core was initialized.
1173 //PrintDebug("VMX core %u: still waiting for INIT\n",info->vcpu_id);
1176 PrintDebug("VMX core %u initialized\n", info->vcpu_id);
1178 // We'll be paranoid about race conditions here
1179 v3_wait_at_barrier(info);
1183 PrintDebug("VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
1184 info->vcpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base),
1185 info->segments.cs.limit, (void *)(info->rip));
1188 PrintDebug("VMX core %u: Launching VMX VM on logical core %u\n", info->vcpu_id, info->pcpu_id);
1190 v3_start_time(info);
1194 if (info->vm_info->run_state == VM_STOPPED) {
1195 info->core_run_state = CORE_STOPPED;
1199 if (v3_vmx_enter(info) == -1) {
1202 addr_t linear_addr = 0;
1204 info->vm_info->run_state = VM_ERROR;
1206 V3_Print("VMX core %u: VMX ERROR!!\n", info->vcpu_id);
1208 v3_print_guest_state(info);
1210 V3_Print("VMX core %u\n", info->vcpu_id);
1212 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
1214 if (info->mem_mode == PHYSICAL_MEM) {
1215 v3_gpa_to_hva(info, linear_addr, &host_addr);
1216 } else if (info->mem_mode == VIRTUAL_MEM) {
1217 v3_gva_to_hva(info, linear_addr, &host_addr);
1220 V3_Print("VMX core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
1222 V3_Print("VMX core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
1223 v3_dump_mem((uint8_t *)host_addr, 15);
1225 v3_print_stack(info);
1229 print_exit_log(info);
1233 v3_wait_at_barrier(info);
1236 if (info->vm_info->run_state == VM_STOPPED) {
1237 info->core_run_state = CORE_STOPPED;
1241 if ((info->num_exits % 5000) == 0) {
1242 V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
1254 #define VMX_FEATURE_CONTROL_MSR 0x0000003a
1255 #define CPUID_VMX_FEATURES 0x00000005 /* LOCK and VMXON */
1256 #define CPUID_1_ECX_VTXFLAG 0x00000020
1258 int v3_is_vmx_capable() {
1259 v3_msr_t feature_msr;
1260 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1262 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
1264 PrintDebug("ECX: 0x%x\n", ecx);
1266 if (ecx & CPUID_1_ECX_VTXFLAG) {
1267 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
1269 PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
1271 if ((feature_msr.lo & CPUID_VMX_FEATURES) != CPUID_VMX_FEATURES) {
1272 PrintDebug("VMX is locked -- enable in the BIOS\n");
1277 PrintDebug("VMX not supported on this cpu\n");
1285 int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) {
1288 if ((core->shdw_pg_mode == NESTED_PAGING) &&
1289 (v3_mach_type == V3_VMX_EPT_UG_CPU)) {
1292 core->segments.cs.selector = rip << 8;
1293 core->segments.cs.limit = 0xffff;
1294 core->segments.cs.base = rip << 12;
1296 core->vm_regs.rdx = core->vcpu_id;
1297 core->vm_regs.rbx = rip;
1305 void v3_init_vmx_cpu(int cpu_id) {
1306 addr_t vmx_on_region = 0;
1307 extern v3_cpu_arch_t v3_mach_type;
1308 extern v3_cpu_arch_t v3_cpu_types[];
1310 if (v3_mach_type == V3_INVALID_CPU) {
1311 if (v3_init_vmx_hw(&hw_info) == -1) {
1312 PrintError("Could not initialize VMX hardware features on cpu %d\n", cpu_id);
1320 // Setup VMXON Region
1321 vmx_on_region = allocate_vmcs();
1324 if (vmx_on(vmx_on_region) == VMX_SUCCESS) {
1325 V3_Print("VMX Enabled\n");
1326 host_vmcs_ptrs[cpu_id] = vmx_on_region;
1328 V3_Print("VMX already enabled\n");
1329 V3_FreePages((void *)vmx_on_region, 1);
1332 PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
1335 struct vmx_sec_proc_ctrls sec_proc_ctrls;
1336 sec_proc_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.sec_proc_ctrls));
1338 if (sec_proc_ctrls.enable_ept == 0) {
1339 V3_Print("VMX EPT (Nested) Paging not supported\n");
1340 v3_cpu_types[cpu_id] = V3_VMX_CPU;
1341 } else if (sec_proc_ctrls.unrstrct_guest == 0) {
1342 V3_Print("VMX EPT (Nested) Paging supported\n");
1343 v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
1345 V3_Print("VMX EPT (Nested) Paging + Unrestricted guest supported\n");
1346 v3_cpu_types[cpu_id] = V3_VMX_EPT_UG_CPU;
1353 void v3_deinit_vmx_cpu(int cpu_id) {
1354 extern v3_cpu_arch_t v3_cpu_types[];
1355 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
1357 if (host_vmcs_ptrs[cpu_id] != 0) {
1358 V3_Print("Disabling VMX\n");
1360 if (vmx_off() != VMX_SUCCESS) {
1361 PrintError("Error executing VMXOFF\n");
1364 V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1);
1366 host_vmcs_ptrs[cpu_id] = 0;