palacios/src/palacios/vmx.c

   1 /*
   2  * This file is part of the Palacios Virtual Machine Monitor developed
   3  * by the V3VEE Project with funding from the United States National
   4  * Science Foundation and the Department of Energy.
   5  *
   6  * The V3VEE Project is a joint project between Northwestern University
   7  * and the University of New Mexico.  You can find out more at
   8  * http://www.v3vee.org
   9  *
  10  * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
  11  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
  12  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
  13  * All rights reserved.
  14  *
  15  * Author: Peter Dinda <pdinda@northwestern.edu>
  16  *         Jack Lange <jarusl@cs.northwestern.edu>
  17  *
  18  * This is free software.  You are permitted to use,
  19  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
  20  */
  21
  22
  23 #include <palacios/vmx.h>
  24 #include <palacios/vmm.h>
  25 #include <palacios/vmx_handler.h>
  26 #include <palacios/vmcs.h>
  27 #include <palacios/vmx_lowlevel.h>
  28 #include <palacios/vmm_lowlevel.h>
  29 #include <palacios/vmm_ctrl_regs.h>
  30 #include <palacios/vmm_config.h>
  31 #include <palacios/vm_guest_mem.h>
  32 #include <palacios/vmm_direct_paging.h>
  33 #include <palacios/vmx_io.h>
  34 #include <palacios/vmx_msr.h>
  35
  36
  37 #ifndef CONFIG_DEBUG_VMX
  38 #undef PrintDebug
  39 #define PrintDebug(fmt, args...)
  40 #endif
  41
  42
  43 static addr_t host_vmcs_ptrs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
  44
  45
  46
  47 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
  48 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
  49
  50 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
  51     int ret = 0;
  52
  53     ret = vmcs_write(field,val);
  54
  55     if (ret != VMX_SUCCESS) {
  56         PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
  57         return 1;
  58     }
  59
  60     return 0;
  61 }
  62
  63 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
  64     int ret = 0;
  65
  66     ret = vmcs_read(field, val);
  67
  68     if (ret != VMX_SUCCESS) {
  69         PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
  70     }
  71
  72     return ret;
  73 }
  74
  75 #if 0
  76 // For the 32 bit reserved bit fields
  77 // MB1s are in the low 32 bits, MBZs are in the high 32 bits of the MSR
  78 static uint32_t sanitize_bits1(uint32_t msr_num, uint32_t val) {
  79     v3_msr_t mask_msr;
  80
  81     PrintDebug("sanitize_bits1 (MSR:%x)\n", msr_num);
  82
  83     v3_get_msr(msr_num, &mask_msr.hi, &mask_msr.lo);
  84
  85     PrintDebug("MSR %x = %x : %x \n", msr_num, mask_msr.hi, mask_msr.lo);
  86
  87     val |= mask_msr.lo;
  88     val |= mask_msr.hi;
  89
  90     return val;
  91 }
  92
  93
  94
  95 static addr_t sanitize_bits2(uint32_t msr_num0, uint32_t msr_num1, addr_t val) {
  96     v3_msr_t msr0, msr1;
  97     addr_t msr0_val, msr1_val;
  98
  99     PrintDebug("sanitize_bits2 (MSR0=%x, MSR1=%x)\n", msr_num0, msr_num1);
 100
 101     v3_get_msr(msr_num0, &msr0.hi, &msr0.lo);
 102     v3_get_msr(msr_num1, &msr1.hi, &msr1.lo);
 103
 104     // This generates a mask that is the natural bit width of the CPU
 105     msr0_val = msr0.value;
 106     msr1_val = msr1.value;
 107
 108     PrintDebug("MSR %x = %p, %x = %p \n", msr_num0, (void*)msr0_val, msr_num1, (void*)msr1_val);
 109
 110     val |= msr0_val;
 111     val |= msr1_val;
 112
 113     return val;
 114 }
 115
 116
 117
 118 #endif
 119
 120
 121 static addr_t allocate_vmcs() {
 122     reg_ex_t msr;
 123     struct vmcs_data * vmcs_page = NULL;
 124
 125     PrintDebug("Allocating page\n");
 126
 127     vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
 128     memset(vmcs_page, 0, 4096);
 129
 130     v3_get_msr(VMX_BASIC_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
 131
 132     vmcs_page->revision = ((struct vmx_basic_msr*)&msr)->revision;
 133     PrintDebug("VMX Revision: 0x%x\n",vmcs_page->revision);
 134
 135     return (addr_t)V3_PAddr((void *)vmcs_page);
 136 }
 137
 138
 139
 140
 141 static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state) {
 142     int vmx_ret = 0;
 143
 144     PrintDebug("Loading VMCS\n");
 145     vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
 146
 147     if (vmx_ret != VMX_SUCCESS) {
 148         PrintError("VMPTRLD failed\n");
 149         return -1;
 150     }
 151
 152
 153
 154     /******* Setup Host State **********/
 155
 156     /* Cache GDTR, IDTR, and TR in host struct */
 157     addr_t gdtr_base;
 158     struct {
 159         uint16_t selector;
 160         addr_t   base;
 161     } __attribute__((packed)) tmp_seg;
 162
 163
 164     __asm__ __volatile__(
 165                          "sgdt (%0);"
 166                          :
 167                          : "q"(&tmp_seg)
 168                          : "memory"
 169                          );
 170     gdtr_base = tmp_seg.base;
 171     vmx_state->host_state.gdtr.base = gdtr_base;
 172
 173     __asm__ __volatile__(
 174                          "sidt (%0);"
 175                          :
 176                          : "q"(&tmp_seg)
 177                          : "memory"
 178                          );
 179     vmx_state->host_state.idtr.base = tmp_seg.base;
 180
 181     __asm__ __volatile__(
 182                          "str (%0);"
 183                          :
 184                          : "q"(&tmp_seg)
 185                          : "memory"
 186                          );
 187     vmx_state->host_state.tr.selector = tmp_seg.selector;
 188
 189     /* The GDTR *index* is bits 3-15 of the selector. */
 190     struct tss_descriptor * desc = NULL;
 191     desc = (struct tss_descriptor *)(gdtr_base + (8 * (tmp_seg.selector >> 3)));
 192
 193     tmp_seg.base = ((desc->base1) |
 194                     (desc->base2 << 16) |
 195                     (desc->base3 << 24) |
 196 #ifdef __V3_64BIT__
 197                     ((uint64_t)desc->base4 << 32)
 198 #else
 199                     (0)
 200 #endif
 201                     );
 202
 203     vmx_state->host_state.tr.base = tmp_seg.base;
 204
 205
 206
 207     /********** Setup and VMX Control Fields from MSR ***********/
 208     /* Setup IO map */
 209
 210
 211     struct v3_msr tmp_msr;
 212
 213     v3_get_msr(VMX_PINBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 214
 215     /* Add external interrupts, NMI exiting, and virtual NMI */
 216     vmx_state->pin_ctrls.value =  tmp_msr.lo;
 217     vmx_state->pin_ctrls.nmi_exit = 1;
 218     vmx_state->pin_ctrls.ext_int_exit = 1;
 219
 220     v3_get_msr(VMX_PROCBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 221
 222     vmx_state->pri_proc_ctrls.value = tmp_msr.lo;
 223     vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
 224     vmx_state->pri_proc_ctrls.hlt_exit = 1;
 225     vmx_state->pri_proc_ctrls.invlpg_exit = 1;
 226     vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
 227     vmx_state->pri_proc_ctrls.pause_exit = 1;
 228
 229     vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->vm_info->io_map.arch_data));
 230     vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
 231             (addr_t)V3_PAddr(info->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
 232
 233
 234     vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->vm_info->msr_map.arch_data));
 235
 236     v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 237     vmx_state->exit_ctrls.value = tmp_msr.lo;
 238     vmx_state->exit_ctrls.host_64_on = 1;
 239
 240     if ((vmx_state->exit_ctrls.save_efer == 1) || (vmx_state->exit_ctrls.ld_efer == 1)) {
 241         vmx_state->ia32e_avail = 1;
 242     }
 243
 244     v3_get_msr(VMX_ENTRY_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 245     vmx_state->entry_ctrls.value = tmp_msr.lo;
 246
 247     {
 248         struct vmx_exception_bitmap excp_bmap;
 249         excp_bmap.value = 0;
 250
 251         excp_bmap.pf = 1;
 252
 253         vmx_ret |= check_vmcs_write(VMCS_EXCP_BITMAP, excp_bmap.value);
 254     }
 255     /******* Setup VMXAssist guest state ***********/
 256
 257     info->rip = 0xd0000;
 258     info->vm_regs.rsp = 0x80000;
 259
 260     struct rflags * flags = (struct rflags *)&(info->ctrl_regs.rflags);
 261     flags->rsvd1 = 1;
 262
 263     /* Print Control MSRs */
 264     v3_get_msr(VMX_CR0_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 265     PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
 266
 267     v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 268     PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
 269
 270
 271 #define GUEST_CR0 0x80000031
 272 #define GUEST_CR4 0x00002000
 273     info->ctrl_regs.cr0 = GUEST_CR0;
 274     info->ctrl_regs.cr4 = GUEST_CR4;
 275
 276     ((struct cr0_32 *)&(info->shdw_pg_state.guest_cr0))->pe = 1;
 277
 278     /* Setup paging */
 279     if (info->shdw_pg_mode == SHADOW_PAGING) {
 280         PrintDebug("Creating initial shadow page table\n");
 281
 282         if (v3_init_passthrough_pts(info) == -1) {
 283             PrintError("Could not initialize passthrough page tables\n");
 284             return -1;
 285         }
 286
 287 #define CR0_PE 0x00000001
 288 #define CR0_PG 0x80000000
 289
 290
 291         vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG) );
 292         vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
 293
 294         info->ctrl_regs.cr3 = info->direct_map_pt;
 295
 296         // vmx_state->pinbased_ctrls |= NMI_EXIT;
 297
 298         /* Add CR exits */
 299         vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
 300         vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
 301     }
 302
 303     // Setup segment registers
 304     {
 305         struct v3_segment * seg_reg = (struct v3_segment *)&(info->segments);
 306
 307         int i;
 308
 309         for (i = 0; i < 10; i++) {
 310             seg_reg[i].selector = 3 << 3;
 311             seg_reg[i].limit = 0xffff;
 312             seg_reg[i].base = 0x0;
 313         }
 314
 315         info->segments.cs.selector = 2<<3;
 316
 317         /* Set only the segment registers */
 318         for (i = 0; i < 6; i++) {
 319             seg_reg[i].limit = 0xfffff;
 320             seg_reg[i].granularity = 1;
 321             seg_reg[i].type = 3;
 322             seg_reg[i].system = 1;
 323             seg_reg[i].dpl = 0;
 324             seg_reg[i].present = 1;
 325             seg_reg[i].db = 1;
 326         }
 327
 328         info->segments.cs.type = 0xb;
 329
 330         info->segments.ldtr.selector = 0x20;
 331         info->segments.ldtr.type = 2;
 332         info->segments.ldtr.system = 0;
 333         info->segments.ldtr.present = 1;
 334         info->segments.ldtr.granularity = 0;
 335
 336
 337         /************* Map in GDT and vmxassist *************/
 338
 339         uint64_t  gdt[] __attribute__ ((aligned(32))) = {
 340             0x0000000000000000ULL,              /* 0x00: reserved */
 341             0x0000830000000000ULL,              /* 0x08: 32-bit TSS */
 342             //0x0000890000000000ULL,            /* 0x08: 32-bit TSS */
 343             0x00CF9b000000FFFFULL,              /* 0x10: CS 32-bit */
 344             0x00CF93000000FFFFULL,              /* 0x18: DS 32-bit */
 345             0x000082000000FFFFULL,              /* 0x20: LDTR 32-bit */
 346         };
 347
 348 #define VMXASSIST_GDT   0x10000
 349         addr_t vmxassist_gdt = 0;
 350
 351         if (v3_gpa_to_hva(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
 352             PrintError("Could not find VMXASSIST GDT destination\n");
 353             return -1;
 354         }
 355
 356         memcpy((void *)vmxassist_gdt, gdt, sizeof(uint64_t) * 5);
 357
 358         info->segments.gdtr.base = VMXASSIST_GDT;
 359
 360 #define VMXASSIST_TSS   0x40000
 361         uint64_t vmxassist_tss = VMXASSIST_TSS;
 362         gdt[0x08 / sizeof(gdt[0])] |=
 363             ((vmxassist_tss & 0xFF000000) << (56 - 24)) |
 364             ((vmxassist_tss & 0x00FF0000) << (32 - 16)) |
 365             ((vmxassist_tss & 0x0000FFFF) << (16)) |
 366             (8392 - 1);
 367
 368         info->segments.tr.selector = 0x08;
 369         info->segments.tr.base = vmxassist_tss;
 370
 371         //info->segments.tr.type = 0x9;
 372         info->segments.tr.type = 0x3;
 373         info->segments.tr.system = 0;
 374         info->segments.tr.present = 1;
 375         info->segments.tr.granularity = 0;
 376     }
 377
 378     // setup VMXASSIST
 379     {
 380 #define VMXASSIST_START 0x000d0000
 381         extern uint8_t v3_vmxassist_start[];
 382         extern uint8_t v3_vmxassist_end[];
 383         addr_t vmxassist_dst = 0;
 384
 385         if (v3_gpa_to_hva(info, VMXASSIST_START, &vmxassist_dst) == -1) {
 386             PrintError("Could not find VMXASSIST destination\n");
 387             return -1;
 388         }
 389
 390         memcpy((void *)vmxassist_dst, v3_vmxassist_start, v3_vmxassist_end - v3_vmxassist_start);
 391     }
 392
 393     /*** Write all the info to the VMCS ***/
 394
 395 #define DEBUGCTL_MSR 0x1d9
 396     v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 397     vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
 398
 399     info->dbg_regs.dr7 = 0x400;
 400
 401     vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
 402
 403
 404     if (v3_update_vmcs_ctrl_fields(info)) {
 405         PrintError("Could not write control fields!\n");
 406         return -1;
 407     }
 408
 409     if (v3_update_vmcs_host_state(info)) {
 410         PrintError("Could not write host state\n");
 411         return -1;
 412     }
 413
 414
 415     vmx_state->state = VMXASSIST_DISABLED;
 416
 417     return 0;
 418 }
 419
 420 int v3_init_vmx_vmcs(struct guest_info * info, v3_vm_class_t vm_class) {
 421     struct vmx_data * vmx_state = NULL;
 422     int vmx_ret = 0;
 423
 424     vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
 425
 426     PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
 427
 428     PrintDebug("Allocating VMCS\n");
 429     vmx_state->vmcs_ptr_phys = allocate_vmcs();
 430
 431     PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
 432
 433     info->vmm_data = vmx_state;
 434
 435     PrintDebug("Initializing VMCS (addr=%p)\n", info->vmm_data);
 436
 437     // TODO: Fix vmcs fields so they're 32-bit
 438
 439     PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
 440     vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
 441
 442     if (vmx_ret != VMX_SUCCESS) {
 443         PrintError("VMCLEAR failed\n");
 444         return -1;
 445     }
 446
 447     if (vm_class == V3_PC_VM) {
 448         PrintDebug("Initializing VMCS\n");
 449         init_vmcs_bios(info, vmx_state);
 450     } else {
 451         PrintError("Invalid VM Class\n");
 452         return -1;
 453     }
 454
 455     return 0;
 456 }
 457
 458 static int update_irq_exit_state(struct guest_info * info) {
 459     struct vmx_exit_idt_vec_info idt_vec_info;
 460
 461     check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
 462
 463     if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
 464 #ifdef CONFIG_DEBUG_INTERRUPTS
 465         PrintDebug("Calling v3_injecting_intr\n");
 466 #endif
 467         info->intr_core_state.irq_started = 0;
 468         v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
 469     }
 470
 471     return 0;
 472 }
 473
 474 static int update_irq_entry_state(struct guest_info * info) {
 475     struct vmx_exit_idt_vec_info idt_vec_info;
 476     struct vmcs_interrupt_state intr_core_state;
 477     struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
 478
 479     check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
 480     check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
 481
 482     /* Check for pending exceptions to inject */
 483     if (v3_excp_pending(info)) {
 484         struct vmx_entry_int_info int_info;
 485         int_info.value = 0;
 486
 487         // In VMX, almost every exception is hardware
 488         // Software exceptions are pretty much only for breakpoint or overflow
 489         int_info.type = 3;
 490         int_info.vector = v3_get_excp_number(info);
 491
 492         if (info->excp_state.excp_error_code_valid) {
 493             check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
 494             int_info.error_code = 1;
 495
 496 #ifdef CONFIG_DEBUG_INTERRUPTS
 497             PrintDebug("Injecting exception %d with error code %x\n",
 498                     int_info.vector, info->excp_state.excp_error_code);
 499 #endif
 500         }
 501
 502         int_info.valid = 1;
 503 #ifdef CONFIG_DEBUG_INTERRUPTS
 504         PrintDebug("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
 505 #endif
 506         check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
 507
 508         v3_injecting_excp(info, int_info.vector);
 509
 510     } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
 511                (intr_core_state.val == 0)) {
 512
 513         if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
 514
 515 #ifdef CONFIG_DEBUG_INTERRUPTS
 516             PrintDebug("IRQ pending from previous injection\n");
 517 #endif
 518
 519             // Copy the IDT vectoring info over to reinject the old interrupt
 520             if (idt_vec_info.error_code == 1) {
 521                 uint32_t err_code = 0;
 522
 523                 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
 524                 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
 525             }
 526
 527             idt_vec_info.undef = 0;
 528             check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
 529
 530         } else {
 531             struct vmx_entry_int_info ent_int;
 532             ent_int.value = 0;
 533
 534             switch (v3_intr_pending(info)) {
 535                 case V3_EXTERNAL_IRQ: {
 536                     info->intr_core_state.irq_vector = v3_get_intr(info);
 537                     ent_int.vector = info->intr_core_state.irq_vector;
 538                     ent_int.type = 0;
 539                     ent_int.error_code = 0;
 540                     ent_int.valid = 1;
 541
 542 #ifdef CONFIG_DEBUG_INTERRUPTS
 543                     PrintDebug("Injecting Interrupt %d at exit %u(EIP=%p)\n",
 544                                info->intr_core_state.irq_vector,
 545                                (uint32_t)info->num_exits,
 546                                (void *)(addr_t)info->rip);
 547 #endif
 548
 549                     check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
 550                     info->intr_core_state.irq_started = 1;
 551
 552                     break;
 553                 }
 554                 case V3_NMI:
 555                     PrintDebug("Injecting NMI\n");
 556
 557                     ent_int.type = 2;
 558                     ent_int.vector = 2;
 559                     ent_int.valid = 1;
 560                     check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
 561
 562                     break;
 563                 case V3_SOFTWARE_INTR:
 564                     PrintDebug("Injecting software interrupt\n");
 565                     ent_int.type = 4;
 566
 567                     ent_int.valid = 1;
 568                     check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
 569
 570                     break;
 571                 case V3_VIRTUAL_IRQ:
 572                     // Not sure what to do here, Intel doesn't have virtual IRQs
 573                     // May be the same as external interrupts/IRQs
 574
 575                     break;
 576                 case V3_INVALID_INTR:
 577                 default:
 578                     break;
 579             }
 580         }
 581     } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
 582         // Enable INTR window exiting so we know when IF=1
 583         uint32_t instr_len;
 584
 585         check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
 586
 587 #ifdef CONFIG_DEBUG_INTERRUPTS
 588         PrintDebug("Enabling Interrupt-Window exiting: %d\n", instr_len);
 589 #endif
 590
 591         vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
 592         check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
 593     }
 594
 595
 596     return 0;
 597 }
 598
 599
 600
 601 static struct vmx_exit_info exit_log[10];
 602
 603 static void print_exit_log(struct guest_info * info) {
 604     int cnt = info->num_exits % 10;
 605     int i = 0;
 606
 607
 608     V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
 609
 610     for (i = 0; i < 10; i++) {
 611         struct vmx_exit_info * tmp = &exit_log[cnt];
 612
 613         V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
 614         V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
 615         V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
 616         V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
 617         V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
 618
 619         cnt--;
 620
 621         if (cnt == -1) {
 622             cnt = 9;
 623         }
 624
 625     }
 626
 627 }
 628
 629 /*
 630  * CAUTION and DANGER!!!
 631  *
 632  * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
 633  * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
 634  * on its contents will cause things to break. The contents at the time of the exit WILL
 635  * change before the exit handler is executed.
 636  */
 637 int v3_vmx_enter(struct guest_info * info) {
 638     int ret = 0;
 639     uint32_t tsc_offset_low, tsc_offset_high;
 640     struct vmx_exit_info exit_info;
 641
 642     // Conditionally yield the CPU if the timeslice has expired
 643     v3_yield_cond(info);
 644
 645     // v3_print_guest_state(info);
 646
 647     // disable global interrupts for vm state transition
 648     v3_disable_ints();
 649
 650     v3_vmx_restore_vmcs(info);
 651
 652
 653 #ifdef CONFIG_SYMCALL
 654     if (info->sym_core_state.symcall_state.sym_call_active == 0) {
 655         update_irq_entry_state(info);
 656     }
 657 #else
 658     update_irq_entry_state(info);
 659 #endif
 660
 661     {
 662         addr_t guest_cr3;
 663         vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
 664         vmcs_write(VMCS_GUEST_CR3, guest_cr3);
 665     }
 666
 667     v3_update_timers(info);
 668     v3_resume_time(info);
 669
 670     tsc_offset_high =
 671         (uint32_t)((info->time_state.host_offset >> 32) & 0xffffffff);
 672     tsc_offset_low = (uint32_t)(info->time_state.host_offset & 0xffffffff);
 673     check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
 674     check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
 675     PrintDebug("Stored 0x %x %x into vmcs TSC offset.\n",
 676                tsc_offset_high, tsc_offset_low);
 677     if (info->vm_info->run_state == VM_STOPPED) {
 678         info->vm_info->run_state = VM_RUNNING;
 679         ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
 680     } else {
 681         ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
 682     }
 683
 684     //  PrintDebug("VMX Exit: ret=%d\n", ret);
 685
 686     if (ret != VMX_SUCCESS) {
 687         uint32_t error = 0;
 688
 689         vmcs_read(VMCS_INSTR_ERR, &error);
 690         PrintError("VMENTRY Error: %d\n", error);
 691
 692         return -1;
 693     }
 694
 695     v3_pause_time(info);
 696 #ifdef OPTION_TIME_MASK_OVERHEAD
 697     v3_offset_time(info, -VMX_ENTRY_OVERHEAD);
 698 #endif
 699
 700     info->num_exits++;
 701
 702     /* Update guest state */
 703     v3_vmx_save_vmcs(info);
 704
 705     // info->cpl = info->segments.cs.selector & 0x3;
 706
 707     info->mem_mode = v3_get_vm_mem_mode(info);
 708     info->cpu_mode = v3_get_vm_cpu_mode(info);
 709
 710
 711     check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
 712     check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
 713     check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
 714     check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
 715     check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
 716     check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
 717     check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
 718
 719     //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
 720
 721     exit_log[info->num_exits % 10] = exit_info;
 722
 723
 724 #ifdef CONFIG_SYMCALL
 725     if (info->sym_core_state.symcall_state.sym_call_active == 0) {
 726         update_irq_exit_state(info);
 727     }
 728 #else
 729     update_irq_exit_state(info);
 730 #endif
 731
 732     // reenable global interrupts after vm exit
 733     v3_enable_ints();
 734
 735     // Conditionally yield the CPU if the timeslice has expired
 736     v3_yield_cond(info);
 737
 738     if (v3_handle_vmx_exit(info, &exit_info) == -1) {
 739         PrintError("Error in VMX exit handler\n");
 740         return -1;
 741     }
 742
 743     return 0;
 744 }
 745
 746
 747 int v3_start_vmx_guest(struct guest_info* info) {
 748
 749
 750     PrintDebug("Launching VMX guest\n");
 751
 752     v3_start_time(info);
 753
 754     while (1) {
 755         if (v3_vmx_enter(info) == -1) {
 756             v3_print_vmcs();
 757             print_exit_log(info);
 758             return -1;
 759         }
 760
 761 /*
 762         if ((info->num_exits % 5000) == 0) {
 763             V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
 764         }
 765 */
 766
 767     }
 768
 769     return 0;
 770 }
 771
 772
 773 int v3_is_vmx_capable() {
 774     v3_msr_t feature_msr;
 775     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 776
 777     v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
 778
 779     PrintDebug("ECX: 0x%x\n", ecx);
 780
 781     if (ecx & CPUID_1_ECX_VTXFLAG) {
 782         v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
 783
 784         PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
 785
 786         if ((feature_msr.lo & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) {
 787             PrintDebug("VMX is locked -- enable in the BIOS\n");
 788             return 0;
 789         }
 790
 791     } else {
 792         PrintDebug("VMX not supported on this cpu\n");
 793         return 0;
 794     }
 795
 796     return 1;
 797 }
 798
 799 static int has_vmx_nested_paging() {
 800     return 0;
 801 }
 802
 803
 804
 805 void v3_init_vmx_cpu(int cpu_id) {
 806     extern v3_cpu_arch_t v3_cpu_types[];
 807     struct v3_msr tmp_msr;
 808     uint64_t ret = 0;
 809
 810     v3_get_msr(VMX_CR4_FIXED0_MSR,&(tmp_msr.hi),&(tmp_msr.lo));
 811 #ifdef __V3_64BIT__
 812     __asm__ __volatile__ (
 813                           "movq %%cr4, %%rbx;"
 814                           "orq  $0x00002000, %%rbx;"
 815                           "movq %%rbx, %0;"
 816                           : "=m"(ret)
 817                           :
 818                           : "%rbx"
 819                           );
 820
 821     if ((~ret & tmp_msr.value) == 0) {
 822         __asm__ __volatile__ (
 823                               "movq %0, %%cr4;"
 824                               :
 825                               : "q"(ret)
 826                               );
 827     } else {
 828         PrintError("Invalid CR4 Settings!\n");
 829         return;
 830     }
 831
 832     __asm__ __volatile__ (
 833                           "movq %%cr0, %%rbx; "
 834                           "orq  $0x00000020,%%rbx; "
 835                           "movq %%rbx, %%cr0;"
 836                           :
 837                           :
 838                           : "%rbx"
 839                           );
 840 #elif __V3_32BIT__
 841     __asm__ __volatile__ (
 842                           "movl %%cr4, %%ecx;"
 843                           "orl  $0x00002000, %%ecx;"
 844                           "movl %%ecx, %0;"
 845                           : "=m"(ret)
 846                           :
 847                           : "%ecx"
 848                           );
 849
 850     if ((~ret & tmp_msr.value) == 0) {
 851         __asm__ __volatile__ (
 852                               "movl %0, %%cr4;"
 853                               :
 854                               : "q"(ret)
 855                               );
 856     } else {
 857         PrintError("Invalid CR4 Settings!\n");
 858         return;
 859     }
 860
 861     __asm__ __volatile__ (
 862                           "movl %%cr0, %%ecx; "
 863                           "orl  $0x00000020,%%ecx; "
 864                           "movl %%ecx, %%cr0;"
 865                           :
 866                           :
 867                           : "%ecx"
 868                           );
 869
 870 #endif
 871
 872     //
 873     // Should check and return Error here....
 874
 875
 876     // Setup VMXON Region
 877     host_vmcs_ptrs[cpu_id] = allocate_vmcs();
 878
 879     PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
 880
 881     if (v3_enable_vmx(host_vmcs_ptrs[cpu_id]) == VMX_SUCCESS) {
 882         PrintDebug("VMX Enabled\n");
 883     } else {
 884         PrintError("VMX initialization failure\n");
 885         return;
 886     }
 887
 888
 889     if (has_vmx_nested_paging() == 1) {
 890         v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
 891     } else {
 892         v3_cpu_types[cpu_id] = V3_VMX_CPU;
 893     }
 894
 895 }
 896