Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


d79693bbb48f924365500e71cff1fab2ad856ad9
[palacios.git] / palacios / src / palacios / vmm_direct_paging_64.h
1 /*
2  * This file is part of the Palacios Virtual Machine Monitor developed
3  * by the V3VEE Project with funding from the United States National
4  * Science Foundation and the Department of Energy.
5  *
6  * The V3VEE Project is a joint project between Northwestern University
7  * and the University of New Mexico.  You can find out more at
8  * http://www.v3vee.org
9  *
10  * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13  * All rights reserved.
14  *
15  * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
16  *
17  * This is free software.  You are permitted to use,
18  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
19  */
20
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
23
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
29
30
31 static inline int handle_passthrough_pagefault_64(struct guest_info * info, 
32                                                      addr_t fault_addr, 
33                                                      pf_error_t error_code) {
34     pml4e64_t * pml = NULL;
35     pdpe64_t * pdpe = NULL;
36     pde64_t * pde = NULL;
37     pte64_t * pte = NULL;
38     addr_t host_addr = 0;
39
40     int pml_index = PML4E64_INDEX(fault_addr);
41     int pdpe_index = PDPE64_INDEX(fault_addr);
42     int pde_index = PDE64_INDEX(fault_addr);
43     int pte_index = PTE64_INDEX(fault_addr);
44
45
46     struct v3_shadow_region * region =  v3_get_shadow_region(info, fault_addr);
47   
48     if ((region == NULL) || 
49         (region->host_type == SHDW_REGION_INVALID)) {
50         PrintError("Invalid region in passthrough page fault 64, addr=%p\n", 
51                    (void *)fault_addr);
52         return -1;
53     }
54
55     host_addr = v3_get_shadow_addr(region, fault_addr);
56
57     // Lookup the correct PML address based on the PAGING MODE
58     if (info->shdw_pg_mode == SHADOW_PAGING) {
59         pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
60     } else {
61         pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
62     }
63
64     //Fix up the PML entry
65     if (pml[pml_index].present == 0) {
66         pdpe = (pdpe64_t *)create_generic_pt_page();
67    
68         pml[pml_index].present = 1;
69         // Set default PML Flags...
70         pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));    
71     } else {
72         pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
73     }
74
75     // Fix up the PDPE entry
76     if (pdpe[pdpe_index].present == 0) {
77         pde = (pde64_t *)create_generic_pt_page();
78         
79         pdpe[pdpe_index].present = 1;
80         // Set default PDPE Flags...
81         pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));    
82     } else {
83         pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
84     }
85
86
87     // Fix up the PDE entry
88     if (pde[pde_index].present == 0) {
89         pte = (pte64_t *)create_generic_pt_page();
90         
91         pde[pde_index].present = 1;
92         pde[pde_index].writable = 1;
93         pde[pde_index].user_page = 1;
94         
95         pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
96     } else {
97         pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
98     }
99
100
101     // Fix up the PTE entry
102     if (pte[pte_index].present == 0) {
103         pte[pte_index].user_page = 1;
104         
105         if (region->host_type == SHDW_REGION_ALLOCATED) {
106             // Full access
107             pte[pte_index].present = 1;
108             pte[pte_index].writable = 1;
109
110             pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
111             
112         } else if (region->host_type == SHDW_REGION_WRITE_HOOK) {
113             // Only trap writes
114             pte[pte_index].present = 1; 
115             pte[pte_index].writable = 0;
116
117             pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
118
119         } else if (region->host_type == SHDW_REGION_FULL_HOOK) {
120             // trap all accesses
121             return v3_handle_mem_full_hook(info, fault_addr, fault_addr, region, error_code);
122
123         } else {
124             PrintError("Unknown Region Type...\n");
125             return -1;
126         }
127     }
128    
129     if ( (region->host_type == SHDW_REGION_WRITE_HOOK) && 
130          (error_code.write == 1) ) {
131         return v3_handle_mem_wr_hook(info, fault_addr, fault_addr, region, error_code);
132     }
133
134     return 0;
135 }
136
137
138 #endif