Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


changed memory map to be layered on top of a single contiguous allocation
[palacios.git] / palacios / src / palacios / vmm_direct_paging_64.h
1 /*
2  * This file is part of the Palacios Virtual Machine Monitor developed
3  * by the V3VEE Project with funding from the United States National
4  * Science Foundation and the Department of Energy.
5  *
6  * The V3VEE Project is a joint project between Northwestern University
7  * and the University of New Mexico.  You can find out more at
8  * http://www.v3vee.org
9  *
10  * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13  * All rights reserved.
14  *
15  * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
16  *
17  * This is free software.  You are permitted to use,
18  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
19  */
20
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
23
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
29
30
31
32 static inline int handle_passthrough_pagefault_64(struct guest_info * info, 
33                                                      addr_t fault_addr, 
34                                                      pf_error_t error_code) {
35     pml4e64_t * pml = NULL;
36     pdpe64_t * pdpe = NULL;
37     pde64_t * pde = NULL;
38     pte64_t * pte = NULL;
39     addr_t host_addr = 0;
40
41     int pml_index = PML4E64_INDEX(fault_addr);
42     int pdpe_index = PDPE64_INDEX(fault_addr);
43     int pde_index = PDE64_INDEX(fault_addr);
44     int pte_index = PTE64_INDEX(fault_addr);
45
46
47     
48
49     struct v3_shadow_region * region =  v3_get_shadow_region(info, fault_addr);
50   
51     if (region == NULL) {
52         PrintError("Invalid region in passthrough page fault 64, addr=%p\n", 
53                    (void *)fault_addr);
54         return -1;
55     }
56
57     host_addr = v3_get_shadow_addr(region, fault_addr);
58     //
59
60     // Lookup the correct PML address based on the PAGING MODE
61     if (info->shdw_pg_mode == SHADOW_PAGING) {
62         pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
63     } else {
64         pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
65     }
66
67     //Fix up the PML entry
68     if (pml[pml_index].present == 0) {
69         pdpe = (pdpe64_t *)create_generic_pt_page();
70    
71         // Set default PML Flags...
72         pml[pml_index].present = 1;
73         pml[pml_index].writable = 1;
74         pml[pml_index].user_page = 1;
75
76         pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));    
77     } else {
78         pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
79     }
80
81     // Fix up the PDPE entry
82     if (pdpe[pdpe_index].present == 0) {
83         pde = (pde64_t *)create_generic_pt_page();
84         
85         // Set default PDPE Flags...
86         pdpe[pdpe_index].present = 1;
87         pdpe[pdpe_index].writable = 1;
88         pdpe[pdpe_index].user_page = 1;
89
90         pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));    
91     } else {
92         pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
93     }
94
95
96     // Fix up the PDE entry
97     if (pde[pde_index].present == 0) {
98         pte = (pte64_t *)create_generic_pt_page();
99         
100         pde[pde_index].present = 1;
101         pde[pde_index].writable = 1;
102         pde[pde_index].user_page = 1;
103         
104         pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
105     } else {
106         pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
107     }
108
109
110     // Fix up the PTE entry
111     if (pte[pte_index].present == 0) {
112         pte[pte_index].user_page = 1;
113         
114         if (region->host_type == SHDW_REGION_ALLOCATED) {
115             // Full access
116             pte[pte_index].present = 1;
117             pte[pte_index].writable = 1;
118
119             pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
120             
121         } else if (region->host_type == SHDW_REGION_WRITE_HOOK) {
122             // Only trap writes
123             pte[pte_index].present = 1; 
124             pte[pte_index].writable = 0;
125
126             pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
127
128         } else if (region->host_type == SHDW_REGION_FULL_HOOK) {
129             // trap all accesses
130             return v3_handle_mem_full_hook(info, fault_addr, fault_addr, region, error_code);
131
132         } else {
133             PrintError("Unknown Region Type...\n");
134             return -1;
135         }
136     }
137    
138     if ( (region->host_type == SHDW_REGION_WRITE_HOOK) && 
139          (error_code.write == 1) ) {
140         return v3_handle_mem_wr_hook(info, fault_addr, fault_addr, region, error_code);
141     }
142
143     return 0;
144 }
145
146
147 #endif