Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


fixed debug flags for direct paging
[palacios.git] / palacios / src / palacios / vmm_direct_paging_64.h
1 /*
2  * This file is part of the Palacios Virtual Machine Monitor developed
3  * by the V3VEE Project with funding from the United States National
4  * Science Foundation and the Department of Energy.
5  *
6  * The V3VEE Project is a joint project between Northwestern University
7  * and the University of New Mexico.  You can find out more at
8  * http://www.v3vee.org
9  *
10  * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13  * All rights reserved.
14  *
15  * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
16  *
17  * This is free software.  You are permitted to use,
18  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
19  */
20
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
23
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
29
30
31
32 static inline int handle_passthrough_pagefault_64(struct guest_info * info, 
33                                                      addr_t fault_addr, 
34                                                      pf_error_t error_code) {
35     pml4e64_t * pml = NULL;
36     pdpe64_t * pdpe = NULL;
37     pde64_t * pde = NULL;
38     pte64_t * pte = NULL;
39     addr_t host_addr = 0;
40
41     int pml_index = PML4E64_INDEX(fault_addr);
42     int pdpe_index = PDPE64_INDEX(fault_addr);
43     int pde_index = PDE64_INDEX(fault_addr);
44     int pte_index = PTE64_INDEX(fault_addr);
45
46
47     
48
49     struct v3_shadow_region * region =  v3_get_shadow_region(info, fault_addr);
50   
51     if ((region == NULL) || 
52         (region->host_type == SHDW_REGION_INVALID)) {
53         PrintError("Invalid region in passthrough page fault 64, addr=%p\n", 
54                    (void *)fault_addr);
55         return -1;
56     }
57
58     host_addr = v3_get_shadow_addr(region, fault_addr);
59     //
60
61     // Lookup the correct PML address based on the PAGING MODE
62     if (info->shdw_pg_mode == SHADOW_PAGING) {
63         pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
64     } else {
65         pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
66     }
67
68     //Fix up the PML entry
69     if (pml[pml_index].present == 0) {
70         pdpe = (pdpe64_t *)create_generic_pt_page();
71    
72         // Set default PML Flags...
73         pml[pml_index].present = 1;
74         pml[pml_index].writable = 1;
75         pml[pml_index].user_page = 1;
76
77         pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));    
78     } else {
79         pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
80     }
81
82     // Fix up the PDPE entry
83     if (pdpe[pdpe_index].present == 0) {
84         pde = (pde64_t *)create_generic_pt_page();
85         
86         // Set default PDPE Flags...
87         pdpe[pdpe_index].present = 1;
88         pdpe[pdpe_index].writable = 1;
89         pdpe[pdpe_index].user_page = 1;
90
91         pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));    
92     } else {
93         pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
94     }
95
96
97     // Fix up the PDE entry
98     if (pde[pde_index].present == 0) {
99         pte = (pte64_t *)create_generic_pt_page();
100         
101         pde[pde_index].present = 1;
102         pde[pde_index].writable = 1;
103         pde[pde_index].user_page = 1;
104         
105         pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
106     } else {
107         pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
108     }
109
110
111     // Fix up the PTE entry
112     if (pte[pte_index].present == 0) {
113         pte[pte_index].user_page = 1;
114         
115         if (region->host_type == SHDW_REGION_ALLOCATED) {
116             // Full access
117             pte[pte_index].present = 1;
118             pte[pte_index].writable = 1;
119
120             pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
121             
122         } else if (region->host_type == SHDW_REGION_WRITE_HOOK) {
123             // Only trap writes
124             pte[pte_index].present = 1; 
125             pte[pte_index].writable = 0;
126
127             pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
128
129         } else if (region->host_type == SHDW_REGION_FULL_HOOK) {
130             // trap all accesses
131             return v3_handle_mem_full_hook(info, fault_addr, fault_addr, region, error_code);
132
133         } else {
134             PrintError("Unknown Region Type...\n");
135             return -1;
136         }
137     }
138    
139     if ( (region->host_type == SHDW_REGION_WRITE_HOOK) && 
140          (error_code.write == 1) ) {
141         return v3_handle_mem_wr_hook(info, fault_addr, fault_addr, region, error_code);
142     }
143
144     return 0;
145 }
146
147
148 #endif