palacios/src/palacios/svm.c

   1 /*
   2  * This file is part of the Palacios Virtual Machine Monitor developed
   3  * by the V3VEE Project with funding from the United States National
   4  * Science Foundation and the Department of Energy.
   5  *
   6  * The V3VEE Project is a joint project between Northwestern University
   7  * and the University of New Mexico.  You can find out more at
   8  * http://www.v3vee.org
   9  *
  10  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
  11  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
  12  * All rights reserved.
  13  *
  14  * Author: Jack Lange <jarusl@cs.northwestern.edu>
  15  *
  16  * This is free software.  You are permitted to use,
  17  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
  18  */
  19
  20
  21 #include <palacios/svm.h>
  22 #include <palacios/vmm.h>
  23
  24 #include <palacios/vmcb.h>
  25 #include <palacios/vmm_mem.h>
  26 #include <palacios/vmm_paging.h>
  27 #include <palacios/svm_handler.h>
  28
  29 #include <palacios/vmm_debug.h>
  30 #include <palacios/vm_guest_mem.h>
  31
  32 #include <palacios/vmm_decoder.h>
  33 #include <palacios/vmm_string.h>
  34 #include <palacios/vmm_lowlevel.h>
  35 #include <palacios/svm_msr.h>
  36
  37 #include <palacios/vmm_rbtree.h>
  38
  39 #include <palacios/vmm_direct_paging.h>
  40
  41 #include <palacios/vmm_ctrl_regs.h>
  42 #include <palacios/svm_io.h>
  43
  44 #include <palacios/vmm_sprintf.h>
  45
  46
  47 uint32_t v3_last_exit;
  48
  49 // This is a global pointer to the host's VMCB
  50 static addr_t host_vmcbs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
  51
  52
  53
  54 extern void v3_stgi();
  55 extern void v3_clgi();
  56 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
  57 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
  58
  59
  60 static vmcb_t * Allocate_VMCB() {
  61     vmcb_t * vmcb_page = (vmcb_t *)V3_VAddr(V3_AllocPages(1));
  62
  63     memset(vmcb_page, 0, 4096);
  64
  65     return vmcb_page;
  66 }
  67
  68
  69
  70 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info * core) {
  71     vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
  72     vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
  73     uint_t i;
  74
  75
  76     //
  77
  78
  79     ctrl_area->svm_instrs.VMRUN = 1;
  80     ctrl_area->svm_instrs.VMMCALL = 1;
  81     ctrl_area->svm_instrs.VMLOAD = 1;
  82     ctrl_area->svm_instrs.VMSAVE = 1;
  83     ctrl_area->svm_instrs.STGI = 1;
  84     ctrl_area->svm_instrs.CLGI = 1;
  85     ctrl_area->svm_instrs.SKINIT = 1;
  86     ctrl_area->svm_instrs.RDTSCP = 1;
  87     ctrl_area->svm_instrs.ICEBP = 1;
  88     ctrl_area->svm_instrs.WBINVD = 1;
  89     ctrl_area->svm_instrs.MONITOR = 1;
  90     ctrl_area->svm_instrs.MWAIT_always = 1;
  91     ctrl_area->svm_instrs.MWAIT_if_armed = 1;
  92     ctrl_area->instrs.INVLPGA = 1;
  93     ctrl_area->instrs.CPUID = 1;
  94
  95     ctrl_area->instrs.HLT = 1;
  96     // guest_state->cr0 = 0x00000001;    // PE
  97
  98     /*
  99       ctrl_area->exceptions.de = 1;
 100       ctrl_area->exceptions.df = 1;
 101
 102       ctrl_area->exceptions.ts = 1;
 103       ctrl_area->exceptions.ss = 1;
 104       ctrl_area->exceptions.ac = 1;
 105       ctrl_area->exceptions.mc = 1;
 106       ctrl_area->exceptions.gp = 1;
 107       ctrl_area->exceptions.ud = 1;
 108       ctrl_area->exceptions.np = 1;
 109       ctrl_area->exceptions.of = 1;
 110
 111       ctrl_area->exceptions.nmi = 1;
 112     */
 113
 114
 115     ctrl_area->instrs.NMI = 1;
 116     ctrl_area->instrs.SMI = 1;
 117     ctrl_area->instrs.INIT = 1;
 118     ctrl_area->instrs.PAUSE = 1;
 119     ctrl_area->instrs.shutdown_evts = 1;
 120
 121
 122     /* DEBUG FOR RETURN CODE */
 123     ctrl_area->exit_code = 1;
 124
 125
 126     /* Setup Guest Machine state */
 127
 128     core->vm_regs.rsp = 0x00;
 129     core->rip = 0xfff0;
 130
 131     core->vm_regs.rdx = 0x00000f00;
 132
 133
 134     core->cpl = 0;
 135
 136     core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
 137     core->ctrl_regs.cr0 = 0x60010010; // Set the WP flag so the memory hooks work in real-mode
 138     core->ctrl_regs.efer |= EFER_MSR_svm_enable;
 139
 140
 141
 142
 143
 144     core->segments.cs.selector = 0xf000;
 145     core->segments.cs.limit = 0xffff;
 146     core->segments.cs.base = 0x0000000f0000LL;
 147
 148     // (raw attributes = 0xf3)
 149     core->segments.cs.type = 0x3;
 150     core->segments.cs.system = 0x1;
 151     core->segments.cs.dpl = 0x3;
 152     core->segments.cs.present = 1;
 153
 154
 155
 156     struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
 157                                       &(core->segments.es), &(core->segments.fs),
 158                                       &(core->segments.gs), NULL};
 159
 160     for ( i = 0; segregs[i] != NULL; i++) {
 161         struct v3_segment * seg = segregs[i];
 162
 163         seg->selector = 0x0000;
 164         //    seg->base = seg->selector << 4;
 165         seg->base = 0x00000000;
 166         seg->limit = ~0u;
 167
 168         // (raw attributes = 0xf3)
 169         seg->type = 0x3;
 170         seg->system = 0x1;
 171         seg->dpl = 0x3;
 172         seg->present = 1;
 173     }
 174
 175     core->segments.gdtr.limit = 0x0000ffff;
 176     core->segments.gdtr.base = 0x0000000000000000LL;
 177     core->segments.idtr.limit = 0x0000ffff;
 178     core->segments.idtr.base = 0x0000000000000000LL;
 179
 180     core->segments.ldtr.selector = 0x0000;
 181     core->segments.ldtr.limit = 0x0000ffff;
 182     core->segments.ldtr.base = 0x0000000000000000LL;
 183     core->segments.tr.selector = 0x0000;
 184     core->segments.tr.limit = 0x0000ffff;
 185     core->segments.tr.base = 0x0000000000000000LL;
 186
 187
 188     core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
 189     core->dbg_regs.dr7 = 0x0000000000000400LL;
 190
 191
 192     ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->io_map.arch_data);
 193     ctrl_area->instrs.IOIO_PROT = 1;
 194
 195     ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data);
 196     ctrl_area->instrs.MSR_PROT = 1;
 197
 198
 199     PrintDebug("Exiting on interrupts\n");
 200     ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
 201     ctrl_area->instrs.INTR = 1;
 202
 203
 204     if (core->shdw_pg_mode == SHADOW_PAGING) {
 205         PrintDebug("Creating initial shadow page table\n");
 206
 207         /* JRL: This is a performance killer, and a simplistic solution */
 208         /* We need to fix this */
 209         ctrl_area->TLB_CONTROL = 1;
 210         ctrl_area->guest_ASID = 1;
 211
 212
 213         if (v3_init_passthrough_pts(core) == -1) {
 214             PrintError("Could not initialize passthrough page tables\n");
 215             return ;
 216         }
 217
 218
 219         core->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
 220         PrintDebug("Created\n");
 221
 222         core->ctrl_regs.cr0 |= 0x80000000;
 223         core->ctrl_regs.cr3 = core->direct_map_pt;
 224
 225         ctrl_area->cr_reads.cr0 = 1;
 226         ctrl_area->cr_writes.cr0 = 1;
 227         //ctrl_area->cr_reads.cr4 = 1;
 228         ctrl_area->cr_writes.cr4 = 1;
 229         ctrl_area->cr_reads.cr3 = 1;
 230         ctrl_area->cr_writes.cr3 = 1;
 231
 232         v3_hook_msr(core->vm_info, EFER_MSR,
 233                     &v3_handle_efer_read,
 234                     &v3_handle_efer_write,
 235                     core);
 236
 237         ctrl_area->instrs.INVLPG = 1;
 238
 239         ctrl_area->exceptions.pf = 1;
 240
 241         guest_state->g_pat = 0x7040600070406ULL;
 242
 243
 244
 245     } else if (core->shdw_pg_mode == NESTED_PAGING) {
 246         // Flush the TLB on entries/exits
 247         ctrl_area->TLB_CONTROL = 1;
 248         ctrl_area->guest_ASID = 1;
 249
 250         // Enable Nested Paging
 251         ctrl_area->NP_ENABLE = 1;
 252
 253         PrintDebug("NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
 254
 255         // Set the Nested Page Table pointer
 256         if (v3_init_passthrough_pts(core) == -1) {
 257             PrintError("Could not initialize Nested page tables\n");
 258             return ;
 259         }
 260
 261         ctrl_area->N_CR3 = core->direct_map_pt;
 262
 263         guest_state->g_pat = 0x7040600070406ULL;
 264     }
 265 }
 266
 267
 268 int v3_init_svm_vmcb(struct guest_info * info, v3_vm_class_t vm_class) {
 269
 270     PrintDebug("Allocating VMCB\n");
 271     info->vmm_data = (void*)Allocate_VMCB();
 272
 273     if (vm_class == V3_PC_VM) {
 274         PrintDebug("Initializing VMCB (addr=%p)\n", (void *)info->vmm_data);
 275         Init_VMCB_BIOS((vmcb_t*)(info->vmm_data), info);
 276     } else {
 277         PrintError("Invalid VM class\n");
 278         return -1;
 279     }
 280
 281     return 0;
 282 }
 283
 284
 285
 286 static int update_irq_exit_state(struct guest_info * info) {
 287     vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
 288
 289     if ((info->intr_core_state.irq_pending == 1) && (guest_ctrl->guest_ctrl.V_IRQ == 0)) {
 290
 291 #ifdef CONFIG_DEBUG_INTERRUPTS
 292         PrintDebug("INTAK cycle completed for irq %d\n", info->intr_core_state.irq_vector);
 293 #endif
 294
 295         info->intr_core_state.irq_started = 1;
 296         info->intr_core_state.irq_pending = 0;
 297
 298         v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
 299     }
 300
 301     if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 0)) {
 302 #ifdef CONFIG_DEBUG_INTERRUPTS
 303         PrintDebug("Interrupt %d taken by guest\n", info->intr_core_state.irq_vector);
 304 #endif
 305
 306         // Interrupt was taken fully vectored
 307         info->intr_core_state.irq_started = 0;
 308
 309     } else {
 310 #ifdef CONFIG_DEBUG_INTERRUPTS
 311         PrintDebug("EXIT INT INFO is set (vec=%d)\n", guest_ctrl->exit_int_info.vector);
 312 #endif
 313     }
 314
 315     return 0;
 316 }
 317
 318
 319 static int update_irq_entry_state(struct guest_info * info) {
 320     vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
 321
 322     if (v3_excp_pending(info)) {
 323         uint_t excp = v3_get_excp_number(info);
 324
 325         guest_ctrl->EVENTINJ.type = SVM_INJECTION_EXCEPTION;
 326
 327         if (info->excp_state.excp_error_code_valid) {
 328             guest_ctrl->EVENTINJ.error_code = info->excp_state.excp_error_code;
 329             guest_ctrl->EVENTINJ.ev = 1;
 330 #ifdef CONFIG_DEBUG_INTERRUPTS
 331             PrintDebug("Injecting exception %d with error code %x\n", excp, guest_ctrl->EVENTINJ.error_code);
 332 #endif
 333         }
 334
 335         guest_ctrl->EVENTINJ.vector = excp;
 336
 337         guest_ctrl->EVENTINJ.valid = 1;
 338
 339 #ifdef CONFIG_DEBUG_INTERRUPTS
 340         PrintDebug("<%d> Injecting Exception %d (CR2=%p) (EIP=%p)\n",
 341                    (int)info->num_exits,
 342                    guest_ctrl->EVENTINJ.vector,
 343                    (void *)(addr_t)info->ctrl_regs.cr2,
 344                    (void *)(addr_t)info->rip);
 345 #endif
 346
 347         v3_injecting_excp(info, excp);
 348     } else if (info->intr_core_state.irq_started == 1) {
 349 #ifdef CONFIG_DEBUG_INTERRUPTS
 350         PrintDebug("IRQ pending from previous injection\n");
 351 #endif
 352         guest_ctrl->guest_ctrl.V_IRQ = 1;
 353         guest_ctrl->guest_ctrl.V_INTR_VECTOR = info->intr_core_state.irq_vector;
 354         guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
 355         guest_ctrl->guest_ctrl.V_INTR_PRIO = 0xf;
 356
 357     } else {
 358         switch (v3_intr_pending(info)) {
 359             case V3_EXTERNAL_IRQ: {
 360                 uint32_t irq = v3_get_intr(info);
 361
 362                 guest_ctrl->guest_ctrl.V_IRQ = 1;
 363                 guest_ctrl->guest_ctrl.V_INTR_VECTOR = irq;
 364                 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
 365                 guest_ctrl->guest_ctrl.V_INTR_PRIO = 0xf;
 366
 367 #ifdef CONFIG_DEBUG_INTERRUPTS
 368                 PrintDebug("Injecting Interrupt %d (EIP=%p)\n",
 369                            guest_ctrl->guest_ctrl.V_INTR_VECTOR,
 370                            (void *)(addr_t)info->rip);
 371 #endif
 372
 373                 info->intr_core_state.irq_pending = 1;
 374                 info->intr_core_state.irq_vector = irq;
 375
 376                 break;
 377             }
 378             case V3_NMI:
 379                 guest_ctrl->EVENTINJ.type = SVM_INJECTION_NMI;
 380                 break;
 381             case V3_SOFTWARE_INTR:
 382                 guest_ctrl->EVENTINJ.type = SVM_INJECTION_SOFT_INTR;
 383                 break;
 384             case V3_VIRTUAL_IRQ:
 385                 guest_ctrl->EVENTINJ.type = SVM_INJECTION_IRQ;
 386                 break;
 387
 388             case V3_INVALID_INTR:
 389             default:
 390                 break;
 391         }
 392
 393     }
 394
 395     return 0;
 396 }
 397
 398
 399 /*
 400  * CAUTION and DANGER!!!
 401  *
 402  * The VMCB CANNOT(!!) be accessed outside of the clgi/stgi calls inside this function
 403  * When exectuing a symbiotic call, the VMCB WILL be overwritten, so any dependencies
 404  * on its contents will cause things to break. The contents at the time of the exit WILL
 405  * change before the exit handler is executed.
 406  */
 407 int v3_svm_enter(struct guest_info * info) {
 408     vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
 409     vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
 410     ullong_t tmp_tsc;
 411     addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
 412
 413     // Conditionally yield the CPU if the timeslice has expired
 414     v3_yield_cond(info);
 415
 416     // disable global interrupts for vm state transition
 417     v3_clgi();
 418
 419     // Synchronize the guest state to the VMCB
 420     guest_state->cr0 = info->ctrl_regs.cr0;
 421     guest_state->cr2 = info->ctrl_regs.cr2;
 422     guest_state->cr3 = info->ctrl_regs.cr3;
 423     guest_state->cr4 = info->ctrl_regs.cr4;
 424     guest_state->dr6 = info->dbg_regs.dr6;
 425     guest_state->dr7 = info->dbg_regs.dr7;
 426     guest_ctrl->guest_ctrl.V_TPR = info->ctrl_regs.cr8 & 0xff;
 427     guest_state->rflags = info->ctrl_regs.rflags;
 428     guest_state->efer = info->ctrl_regs.efer;
 429
 430     guest_state->cpl = info->cpl;
 431
 432     v3_set_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
 433
 434     guest_state->rax = info->vm_regs.rax;
 435     guest_state->rip = info->rip;
 436     guest_state->rsp = info->vm_regs.rsp;
 437
 438 #ifdef CONFIG_SYMBIOTIC
 439     if (info->vm_info->sym_state.symcalls[info->cpu_id].sym_call_active == 0) {
 440         update_irq_entry_state(info);
 441     }
 442 #else
 443     update_irq_entry_state(info);
 444 #endif
 445
 446
 447     /* ** */
 448
 449     /*
 450       PrintDebug("SVM Entry to CS=%p  rip=%p...\n",
 451       (void *)(addr_t)info->segments.cs.base,
 452       (void *)(addr_t)info->rip);
 453     */
 454
 455 #ifdef CONFIG_SYMBIOTIC
 456     if (info->vm_info->sym_state.symcalls[info->cpu_id].sym_call_active == 1) {
 457         if (guest_ctrl->guest_ctrl.V_IRQ == 1) {
 458             V3_Print("!!! Injecting Interrupt during Sym call !!!\n");
 459         }
 460     }
 461 #endif
 462
 463
 464     rdtscll(info->time_state.cached_host_tsc);
 465     guest_ctrl->TSC_OFFSET = info->time_state.guest_tsc - info->time_state.cached_host_tsc;
 466
 467     v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[info->cpu_id]);
 468
 469
 470     v3_last_exit = (uint32_t)(guest_ctrl->exit_code);
 471
 472     //  v3_print_cond("SVM Returned: Exit Code: %x\n", (uint32_t)(guest_ctrl->exit_code));
 473
 474     rdtscll(tmp_tsc);
 475
 476     //PrintDebug("SVM Returned\n");
 477
 478     info->num_exits++;
 479
 480     v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
 481
 482
 483     // Save Guest state from VMCB
 484     info->rip = guest_state->rip;
 485     info->vm_regs.rsp = guest_state->rsp;
 486     info->vm_regs.rax = guest_state->rax;
 487
 488     info->cpl = guest_state->cpl;
 489
 490     info->ctrl_regs.cr0 = guest_state->cr0;
 491     info->ctrl_regs.cr2 = guest_state->cr2;
 492     info->ctrl_regs.cr3 = guest_state->cr3;
 493     info->ctrl_regs.cr4 = guest_state->cr4;
 494     info->dbg_regs.dr6 = guest_state->dr6;
 495     info->dbg_regs.dr7 = guest_state->dr7;
 496     info->ctrl_regs.cr8 = guest_ctrl->guest_ctrl.V_TPR;
 497     info->ctrl_regs.rflags = guest_state->rflags;
 498     info->ctrl_regs.efer = guest_state->efer;
 499
 500     v3_get_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
 501     info->cpu_mode = v3_get_vm_cpu_mode(info);
 502     info->mem_mode = v3_get_vm_mem_mode(info);
 503     /* ** */
 504
 505
 506     // save exit info here
 507     exit_code = guest_ctrl->exit_code;
 508     exit_info1 = guest_ctrl->exit_info1;
 509     exit_info2 = guest_ctrl->exit_info2;
 510
 511
 512 #ifdef CONFIG_SYMBIOTIC
 513     if (info->vm_info->sym_state.symcalls[info->cpu_id].sym_call_active == 0) {
 514         update_irq_exit_state(info);
 515     }
 516 #else
 517     update_irq_exit_state(info);
 518 #endif
 519
 520
 521     // reenable global interrupts after vm exit
 522     v3_stgi();
 523
 524
 525     // Conditionally yield the CPU if the timeslice has expired
 526     v3_yield_cond(info);
 527
 528
 529     if (v3_handle_svm_exit(info, exit_code, exit_info1, exit_info2) != 0) {
 530         PrintError("Error in SVM exit handler\n");
 531         return -1;
 532     }
 533
 534
 535     return 0;
 536 }
 537
 538
 539 int v3_start_svm_guest(struct guest_info *info) {
 540     //    vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
 541     //  vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
 542
 543
 544
 545     PrintDebug("Launching SVM VM (vmcb=%p)\n", (void *)info->vmm_data);
 546     //PrintDebugVMCB((vmcb_t*)(info->vmm_data));
 547
 548     info->vm_info->run_state = VM_RUNNING;
 549     rdtscll(info->yield_start_cycle);
 550
 551
 552     while (1) {
 553         if (v3_svm_enter(info) == -1) {
 554             vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
 555             addr_t host_addr;
 556             addr_t linear_addr = 0;
 557
 558             info->vm_info->run_state = VM_ERROR;
 559
 560             V3_Print("SVM ERROR!!\n");
 561
 562             v3_print_guest_state(info);
 563
 564             V3_Print("SVM Exit Code: %p\n", (void *)(addr_t)guest_ctrl->exit_code);
 565
 566             V3_Print("exit_info1 low = 0x%.8x\n", *(uint_t*)&(guest_ctrl->exit_info1));
 567             V3_Print("exit_info1 high = 0x%.8x\n", *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
 568
 569             V3_Print("exit_info2 low = 0x%.8x\n", *(uint_t*)&(guest_ctrl->exit_info2));
 570             V3_Print("exit_info2 high = 0x%.8x\n", *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
 571
 572             linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
 573
 574             if (info->mem_mode == PHYSICAL_MEM) {
 575                 guest_pa_to_host_va(info, linear_addr, &host_addr);
 576             } else if (info->mem_mode == VIRTUAL_MEM) {
 577                 guest_va_to_host_va(info, linear_addr, &host_addr);
 578             }
 579
 580             V3_Print("Host Address of rip = 0x%p\n", (void *)host_addr);
 581
 582             V3_Print("Instr (15 bytes) at %p:\n", (void *)host_addr);
 583             v3_dump_mem((uint8_t *)host_addr, 15);
 584
 585             v3_print_stack(info);
 586
 587             break;
 588         }
 589
 590 /*
 591         if ((info->num_exits % 5000) == 0) {
 592             V3_Print("SVM Exit number %d\n", (uint32_t)info->num_exits);
 593         }
 594 */
 595
 596     }
 597     return 0;
 598 }
 599
 600
 601
 602
 603
 604 /* Checks machine SVM capability */
 605 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
 606 int v3_is_svm_capable() {
 607     uint_t vm_cr_low = 0, vm_cr_high = 0;
 608     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 609
 610     v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
 611
 612     PrintDebug("CPUID_EXT_FEATURE_IDS_ecx=0x%x\n", ecx);
 613
 614     if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
 615       V3_Print("SVM Not Available\n");
 616       return 0;
 617     }  else {
 618         v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
 619
 620         PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
 621
 622         if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
 623             V3_Print("SVM is available but is disabled.\n");
 624
 625             v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
 626
 627             PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
 628
 629             if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
 630                 V3_Print("SVM BIOS Disabled, not unlockable\n");
 631             } else {
 632                 V3_Print("SVM is locked with a key\n");
 633             }
 634             return 0;
 635
 636         } else {
 637             V3_Print("SVM is available and  enabled.\n");
 638
 639             v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
 640             PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_eax=0x%x\n", eax);
 641             PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ebx=0x%x\n", ebx);
 642             PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ecx=0x%x\n", ecx);
 643             PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
 644
 645             return 1;
 646         }
 647     }
 648 }
 649
 650 static int has_svm_nested_paging() {
 651     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 652
 653     v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
 654
 655     //PrintDebug("CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
 656
 657     if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
 658         V3_Print("SVM Nested Paging not supported\n");
 659         return 0;
 660     } else {
 661         V3_Print("SVM Nested Paging supported\n");
 662         return 1;
 663     }
 664 }
 665
 666
 667 void v3_init_svm_cpu(int cpu_id) {
 668     reg_ex_t msr;
 669     extern v3_cpu_arch_t v3_cpu_types[];
 670
 671     // Enable SVM on the CPU
 672     v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
 673     msr.e_reg.low |= EFER_MSR_svm_enable;
 674     v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
 675
 676     V3_Print("SVM Enabled\n");
 677
 678     // Setup the host state save area
 679     host_vmcbs[cpu_id] = (addr_t)V3_AllocPages(4);
 680
 681     /* 64-BIT-ISSUE */
 682     //  msr.e_reg.high = 0;
 683     //msr.e_reg.low = (uint_t)host_vmcb;
 684     msr.r_reg = host_vmcbs[cpu_id];
 685
 686     PrintDebug("Host State being saved at %p\n", (void *)host_vmcbs[cpu_id]);
 687     v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
 688
 689
 690     if (has_svm_nested_paging() == 1) {
 691         v3_cpu_types[cpu_id] = V3_SVM_REV3_CPU;
 692     } else {
 693         v3_cpu_types[cpu_id] = V3_SVM_CPU;
 694     }
 695 }
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 749
 750 #if 0
 751 /*
 752  * Test VMSAVE/VMLOAD Latency
 753  */
 754 #define vmsave ".byte 0x0F,0x01,0xDB ; "
 755 #define vmload ".byte 0x0F,0x01,0xDA ; "
 756 {
 757     uint32_t start_lo, start_hi;
 758     uint32_t end_lo, end_hi;
 759     uint64_t start, end;
 760
 761     __asm__ __volatile__ (
 762                           "rdtsc ; "
 763                           "movl %%eax, %%esi ; "
 764                           "movl %%edx, %%edi ; "
 765                           "movq  %%rcx, %%rax ; "
 766                           vmsave
 767                           "rdtsc ; "
 768                           : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
 769                           : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
 770                           );
 771
 772     start = start_hi;
 773     start <<= 32;
 774     start += start_lo;
 775
 776     end = end_hi;
 777     end <<= 32;
 778     end += end_lo;
 779
 780     PrintDebug("VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
 781
 782     __asm__ __volatile__ (
 783                           "rdtsc ; "
 784                           "movl %%eax, %%esi ; "
 785                           "movl %%edx, %%edi ; "
 786                           "movq  %%rcx, %%rax ; "
 787                           vmload
 788                           "rdtsc ; "
 789                           : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
 790                               : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
 791                               );
 792
 793         start = start_hi;
 794         start <<= 32;
 795         start += start_lo;
 796
 797         end = end_hi;
 798         end <<= 32;
 799         end += end_lo;
 800
 801
 802         PrintDebug("VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
 803     }
 804     /* End Latency Test */
 805
 806 #endif
 807
 808
 809
 810
 811
 812
 813
 814 #if 0
 815 void Init_VMCB_pe(vmcb_t *vmcb, struct guest_info vm_info) {
 816   vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
 817   vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
 818   uint_t i = 0;
 819
 820
 821   guest_state->rsp = vm_info.vm_regs.rsp;
 822   guest_state->rip = vm_info.rip;
 823
 824
 825   /* I pretty much just gutted this from TVMM */
 826   /* Note: That means its probably wrong */
 827
 828   // set the segment registers to mirror ours
 829   guest_state->cs.selector = 1<<3;
 830   guest_state->cs.attrib.fields.type = 0xa; // Code segment+read
 831   guest_state->cs.attrib.fields.S = 1;
 832   guest_state->cs.attrib.fields.P = 1;
 833   guest_state->cs.attrib.fields.db = 1;
 834   guest_state->cs.attrib.fields.G = 1;
 835   guest_state->cs.limit = 0xfffff;
 836   guest_state->cs.base = 0;
 837
 838   struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
 839   for ( i = 0; segregs[i] != NULL; i++) {
 840     struct vmcb_selector * seg = segregs[i];
 841
 842     seg->selector = 2<<3;
 843     seg->attrib.fields.type = 0x2; // Data Segment+read/write
 844     seg->attrib.fields.S = 1;
 845     seg->attrib.fields.P = 1;
 846     seg->attrib.fields.db = 1;
 847     seg->attrib.fields.G = 1;
 848     seg->limit = 0xfffff;
 849     seg->base = 0;
 850   }
 851
 852
 853   {
 854     /* JRL THIS HAS TO GO */
 855
 856     //    guest_state->tr.selector = GetTR_Selector();
 857     guest_state->tr.attrib.fields.type = 0x9;
 858     guest_state->tr.attrib.fields.P = 1;
 859     // guest_state->tr.limit = GetTR_Limit();
 860     //guest_state->tr.base = GetTR_Base();// - 0x2000;
 861     /* ** */
 862   }
 863
 864
 865   /* ** */
 866
 867
 868   guest_state->efer |= EFER_MSR_svm_enable;
 869   guest_state->rflags = 0x00000002; // The reserved bit is always 1
 870   ctrl_area->svm_instrs.VMRUN = 1;
 871   guest_state->cr0 = 0x00000001;    // PE
 872   ctrl_area->guest_ASID = 1;
 873
 874
 875   //  guest_state->cpl = 0;
 876
 877
 878
 879   // Setup exits
 880
 881   ctrl_area->cr_writes.cr4 = 1;
 882
 883   ctrl_area->exceptions.de = 1;
 884   ctrl_area->exceptions.df = 1;
 885   ctrl_area->exceptions.pf = 1;
 886   ctrl_area->exceptions.ts = 1;
 887   ctrl_area->exceptions.ss = 1;
 888   ctrl_area->exceptions.ac = 1;
 889   ctrl_area->exceptions.mc = 1;
 890   ctrl_area->exceptions.gp = 1;
 891   ctrl_area->exceptions.ud = 1;
 892   ctrl_area->exceptions.np = 1;
 893   ctrl_area->exceptions.of = 1;
 894   ctrl_area->exceptions.nmi = 1;
 895
 896
 897
 898   ctrl_area->instrs.IOIO_PROT = 1;
 899   ctrl_area->IOPM_BASE_PA = (uint_t)V3_AllocPages(3);
 900
 901   {
 902     reg_ex_t tmp_reg;
 903     tmp_reg.r_reg = ctrl_area->IOPM_BASE_PA;
 904     memset((void*)(tmp_reg.e_reg.low), 0xffffffff, PAGE_SIZE * 2);
 905   }
 906
 907   ctrl_area->instrs.INTR = 1;
 908
 909
 910   {
 911     char gdt_buf[6];
 912     char idt_buf[6];
 913
 914     memset(gdt_buf, 0, 6);
 915     memset(idt_buf, 0, 6);
 916
 917
 918     uint_t gdt_base, idt_base;
 919     ushort_t gdt_limit, idt_limit;
 920
 921     GetGDTR(gdt_buf);
 922     gdt_base = *(ulong_t*)((uchar_t*)gdt_buf + 2) & 0xffffffff;
 923     gdt_limit = *(ushort_t*)(gdt_buf) & 0xffff;
 924     PrintDebug("GDT: base: %x, limit: %x\n", gdt_base, gdt_limit);
 925
 926     GetIDTR(idt_buf);
 927     idt_base = *(ulong_t*)(idt_buf + 2) & 0xffffffff;
 928     idt_limit = *(ushort_t*)(idt_buf) & 0xffff;
 929     PrintDebug("IDT: base: %x, limit: %x\n",idt_base, idt_limit);
 930
 931
 932     // gdt_base -= 0x2000;
 933     //idt_base -= 0x2000;
 934
 935     guest_state->gdtr.base = gdt_base;
 936     guest_state->gdtr.limit = gdt_limit;
 937     guest_state->idtr.base = idt_base;
 938     guest_state->idtr.limit = idt_limit;
 939
 940
 941   }
 942
 943
 944   // also determine if CPU supports nested paging
 945   /*
 946   if (vm_info.page_tables) {
 947     //   if (0) {
 948     // Flush the TLB on entries/exits
 949     ctrl_area->TLB_CONTROL = 1;
 950
 951     // Enable Nested Paging
 952     ctrl_area->NP_ENABLE = 1;
 953
 954     PrintDebug("NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
 955
 956         // Set the Nested Page Table pointer
 957     ctrl_area->N_CR3 |= ((addr_t)vm_info.page_tables & 0xfffff000);
 958
 959
 960     //   ctrl_area->N_CR3 = Get_CR3();
 961     // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
 962
 963     guest_state->g_pat = 0x7040600070406ULL;
 964
 965     PrintDebug("Set Nested CR3: lo: 0x%x  hi: 0x%x\n", (uint_t)*(&(ctrl_area->N_CR3)), (uint_t)*((unsigned char *)&(ctrl_area->N_CR3) + 4));
 966     PrintDebug("Set Guest CR3: lo: 0x%x  hi: 0x%x\n", (uint_t)*(&(guest_state->cr3)), (uint_t)*((unsigned char *)&(guest_state->cr3) + 4));
 967     // Enable Paging
 968     //    guest_state->cr0 |= 0x80000000;
 969   }
 970   */
 971
 972 }
 973
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 977
 978 #endif
 979
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