2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/svm.h>
22 #include <palacios/vmm.h>
24 #include <palacios/vmcb.h>
25 #include <palacios/vmm_mem.h>
26 #include <palacios/vmm_paging.h>
27 #include <palacios/svm_handler.h>
29 #include <palacios/vmm_debug.h>
30 #include <palacios/vm_guest_mem.h>
32 #include <palacios/vmm_decoder.h>
33 #include <palacios/vmm_string.h>
34 #include <palacios/vmm_lowlevel.h>
35 #include <palacios/svm_msr.h>
37 #include <palacios/vmm_rbtree.h>
38 #include <palacios/vmm_barrier.h>
40 #ifdef V3_CONFIG_CHECKPOINT
41 #include <palacios/vmm_checkpoint.h>
44 #include <palacios/vmm_direct_paging.h>
46 #include <palacios/vmm_ctrl_regs.h>
47 #include <palacios/svm_io.h>
49 #include <palacios/vmm_sprintf.h>
52 #ifndef V3_CONFIG_DEBUG_SVM
54 #define PrintDebug(fmt, args...)
58 uint32_t v3_last_exit;
60 // This is a global pointer to the host's VMCB
61 static addr_t host_vmcbs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
65 extern void v3_stgi();
66 extern void v3_clgi();
67 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
68 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
71 static vmcb_t * Allocate_VMCB() {
72 vmcb_t * vmcb_page = NULL;
73 addr_t vmcb_pa = (addr_t)V3_AllocPages(1);
75 if ((void *)vmcb_pa == NULL) {
76 PrintError("Error allocating VMCB\n");
80 vmcb_page = (vmcb_t *)V3_VAddr((void *)vmcb_pa);
82 memset(vmcb_page, 0, 4096);
88 static int v3_svm_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data)
92 // Call arch-independent handler
93 if ((status = v3_handle_efer_write(core, msr, src, priv_data)) != 0) {
99 // Ensure that hardware visible EFER.SVME bit is set (SVM Enable)
100 struct efer_64 * hw_efer = (struct efer_64 *)&(core->ctrl_regs.efer);
108 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info * core) {
109 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
110 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
115 ctrl_area->svm_instrs.VMRUN = 1;
116 ctrl_area->svm_instrs.VMMCALL = 1;
117 ctrl_area->svm_instrs.VMLOAD = 1;
118 ctrl_area->svm_instrs.VMSAVE = 1;
119 ctrl_area->svm_instrs.STGI = 1;
120 ctrl_area->svm_instrs.CLGI = 1;
121 ctrl_area->svm_instrs.SKINIT = 1;
122 ctrl_area->svm_instrs.ICEBP = 1;
123 ctrl_area->svm_instrs.WBINVD = 1;
124 ctrl_area->svm_instrs.MONITOR = 1;
125 ctrl_area->svm_instrs.MWAIT_always = 1;
126 ctrl_area->svm_instrs.MWAIT_if_armed = 1;
127 ctrl_area->instrs.INVLPGA = 1;
128 ctrl_area->instrs.CPUID = 1;
130 ctrl_area->instrs.HLT = 1;
132 /* Set at VMM launch as needed */
133 ctrl_area->instrs.RDTSC = 0;
134 ctrl_area->svm_instrs.RDTSCP = 0;
136 // guest_state->cr0 = 0x00000001; // PE
139 ctrl_area->exceptions.de = 1;
140 ctrl_area->exceptions.df = 1;
142 ctrl_area->exceptions.ts = 1;
143 ctrl_area->exceptions.ss = 1;
144 ctrl_area->exceptions.ac = 1;
145 ctrl_area->exceptions.mc = 1;
146 ctrl_area->exceptions.gp = 1;
147 ctrl_area->exceptions.ud = 1;
148 ctrl_area->exceptions.np = 1;
149 ctrl_area->exceptions.of = 1;
151 ctrl_area->exceptions.nmi = 1;
155 ctrl_area->instrs.NMI = 1;
156 ctrl_area->instrs.SMI = 0; // allow SMIs to run in guest
157 ctrl_area->instrs.INIT = 1;
158 // ctrl_area->instrs.PAUSE = 1;
159 ctrl_area->instrs.shutdown_evts = 1;
162 /* DEBUG FOR RETURN CODE */
163 ctrl_area->exit_code = 1;
166 /* Setup Guest Machine state */
168 core->vm_regs.rsp = 0x00;
171 core->vm_regs.rdx = 0x00000f00;
176 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
177 core->ctrl_regs.cr0 = 0x60010010; // Set the WP flag so the memory hooks work in real-mode
178 core->ctrl_regs.efer |= EFER_MSR_svm_enable;
184 core->segments.cs.selector = 0xf000;
185 core->segments.cs.limit = 0xffff;
186 core->segments.cs.base = 0x0000000f0000LL;
188 // (raw attributes = 0xf3)
189 core->segments.cs.type = 0x3;
190 core->segments.cs.system = 0x1;
191 core->segments.cs.dpl = 0x3;
192 core->segments.cs.present = 1;
196 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
197 &(core->segments.es), &(core->segments.fs),
198 &(core->segments.gs), NULL};
200 for ( i = 0; segregs[i] != NULL; i++) {
201 struct v3_segment * seg = segregs[i];
203 seg->selector = 0x0000;
204 // seg->base = seg->selector << 4;
205 seg->base = 0x00000000;
208 // (raw attributes = 0xf3)
215 core->segments.gdtr.limit = 0x0000ffff;
216 core->segments.gdtr.base = 0x0000000000000000LL;
217 core->segments.idtr.limit = 0x0000ffff;
218 core->segments.idtr.base = 0x0000000000000000LL;
220 core->segments.ldtr.selector = 0x0000;
221 core->segments.ldtr.limit = 0x0000ffff;
222 core->segments.ldtr.base = 0x0000000000000000LL;
223 core->segments.tr.selector = 0x0000;
224 core->segments.tr.limit = 0x0000ffff;
225 core->segments.tr.base = 0x0000000000000000LL;
228 core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
229 core->dbg_regs.dr7 = 0x0000000000000400LL;
232 ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->io_map.arch_data);
233 ctrl_area->instrs.IOIO_PROT = 1;
235 ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data);
236 ctrl_area->instrs.MSR_PROT = 1;
239 PrintDebug("Exiting on interrupts\n");
240 ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
241 ctrl_area->instrs.INTR = 1;
244 v3_hook_msr(core->vm_info, EFER_MSR,
245 &v3_handle_efer_read,
246 &v3_svm_handle_efer_write,
249 if (core->shdw_pg_mode == SHADOW_PAGING) {
250 PrintDebug("Creating initial shadow page table\n");
252 /* JRL: This is a performance killer, and a simplistic solution */
253 /* We need to fix this */
254 ctrl_area->TLB_CONTROL = 1;
255 ctrl_area->guest_ASID = 1;
258 if (v3_init_passthrough_pts(core) == -1) {
259 PrintError("Could not initialize passthrough page tables\n");
264 core->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
265 PrintDebug("Created\n");
267 core->ctrl_regs.cr0 |= 0x80000000;
268 core->ctrl_regs.cr3 = core->direct_map_pt;
270 ctrl_area->cr_reads.cr0 = 1;
271 ctrl_area->cr_writes.cr0 = 1;
272 //ctrl_area->cr_reads.cr4 = 1;
273 ctrl_area->cr_writes.cr4 = 1;
274 ctrl_area->cr_reads.cr3 = 1;
275 ctrl_area->cr_writes.cr3 = 1;
279 ctrl_area->instrs.INVLPG = 1;
281 ctrl_area->exceptions.pf = 1;
283 guest_state->g_pat = 0x7040600070406ULL;
287 } else if (core->shdw_pg_mode == NESTED_PAGING) {
288 // Flush the TLB on entries/exits
289 ctrl_area->TLB_CONTROL = 1;
290 ctrl_area->guest_ASID = 1;
292 // Enable Nested Paging
293 ctrl_area->NP_ENABLE = 1;
295 PrintDebug("NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
297 // Set the Nested Page Table pointer
298 if (v3_init_passthrough_pts(core) == -1) {
299 PrintError("Could not initialize Nested page tables\n");
303 ctrl_area->N_CR3 = core->direct_map_pt;
305 guest_state->g_pat = 0x7040600070406ULL;
308 /* tell the guest that we don't support SVM */
309 v3_hook_msr(core->vm_info, SVM_VM_CR_MSR,
310 &v3_handle_vm_cr_read,
311 &v3_handle_vm_cr_write,
316 #define INT_PENDING_AMD_MSR 0xc0010055
318 v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
319 v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
320 v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
321 v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
322 v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
324 v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
325 v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
326 v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
329 v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
330 v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
332 // Passthrough read operations are ok.
333 v3_hook_msr(core->vm_info, INT_PENDING_AMD_MSR, NULL, v3_msr_unhandled_write, NULL);
338 int v3_init_svm_vmcb(struct guest_info * core, v3_vm_class_t vm_class) {
340 PrintDebug("Allocating VMCB\n");
341 core->vmm_data = (void *)Allocate_VMCB();
343 if (core->vmm_data == NULL) {
344 PrintError("Could not allocate VMCB, Exiting...\n");
348 if (vm_class == V3_PC_VM) {
349 PrintDebug("Initializing VMCB (addr=%p)\n", (void *)core->vmm_data);
350 Init_VMCB_BIOS((vmcb_t*)(core->vmm_data), core);
352 PrintError("Invalid VM class\n");
356 core->core_run_state = CORE_STOPPED;
362 int v3_deinit_svm_vmcb(struct guest_info * core) {
363 V3_FreePages(V3_PAddr(core->vmm_data), 1);
368 #ifdef V3_CONFIG_CHECKPOINT
369 int v3_svm_save_core(struct guest_info * core, void * ctx){
371 v3_chkpt_save_8(ctx, "cpl", &(core->cpl));
372 v3_chkpt_save(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data);
377 int v3_svm_load_core(struct guest_info * core, void * ctx){
379 v3_chkpt_load_8(ctx, "cpl", &(core->cpl));
381 if (v3_chkpt_load(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data) == -1) {
389 static int update_irq_exit_state(struct guest_info * info) {
390 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
392 // Fix for QEMU bug using EVENTINJ as an internal cache
393 guest_ctrl->EVENTINJ.valid = 0;
395 if ((info->intr_core_state.irq_pending == 1) && (guest_ctrl->guest_ctrl.V_IRQ == 0)) {
397 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
398 PrintDebug("INTAK cycle completed for irq %d\n", info->intr_core_state.irq_vector);
401 info->intr_core_state.irq_started = 1;
402 info->intr_core_state.irq_pending = 0;
404 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
407 if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 0)) {
408 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
409 PrintDebug("Interrupt %d taken by guest\n", info->intr_core_state.irq_vector);
412 // Interrupt was taken fully vectored
413 info->intr_core_state.irq_started = 0;
415 } else if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 1)) {
416 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
417 PrintDebug("EXIT INT INFO is set (vec=%d)\n", guest_ctrl->exit_int_info.vector);
425 static int update_irq_entry_state(struct guest_info * info) {
426 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
429 if (info->intr_core_state.irq_pending == 0) {
430 guest_ctrl->guest_ctrl.V_IRQ = 0;
431 guest_ctrl->guest_ctrl.V_INTR_VECTOR = 0;
434 if (v3_excp_pending(info)) {
435 uint_t excp = v3_get_excp_number(info);
437 guest_ctrl->EVENTINJ.type = SVM_INJECTION_EXCEPTION;
439 if (info->excp_state.excp_error_code_valid) {
440 guest_ctrl->EVENTINJ.error_code = info->excp_state.excp_error_code;
441 guest_ctrl->EVENTINJ.ev = 1;
442 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
443 PrintDebug("Injecting exception %d with error code %x\n", excp, guest_ctrl->EVENTINJ.error_code);
447 guest_ctrl->EVENTINJ.vector = excp;
449 guest_ctrl->EVENTINJ.valid = 1;
451 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
452 PrintDebug("<%d> Injecting Exception %d (CR2=%p) (EIP=%p)\n",
453 (int)info->num_exits,
454 guest_ctrl->EVENTINJ.vector,
455 (void *)(addr_t)info->ctrl_regs.cr2,
456 (void *)(addr_t)info->rip);
459 v3_injecting_excp(info, excp);
460 } else if (info->intr_core_state.irq_started == 1) {
461 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
462 PrintDebug("IRQ pending from previous injection\n");
464 guest_ctrl->guest_ctrl.V_IRQ = 1;
465 guest_ctrl->guest_ctrl.V_INTR_VECTOR = info->intr_core_state.irq_vector;
466 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
467 guest_ctrl->guest_ctrl.V_INTR_PRIO = 0xf;
470 switch (v3_intr_pending(info)) {
471 case V3_EXTERNAL_IRQ: {
472 uint32_t irq = v3_get_intr(info);
474 guest_ctrl->guest_ctrl.V_IRQ = 1;
475 guest_ctrl->guest_ctrl.V_INTR_VECTOR = irq;
476 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
477 guest_ctrl->guest_ctrl.V_INTR_PRIO = 0xf;
479 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
480 PrintDebug("Injecting Interrupt %d (EIP=%p)\n",
481 guest_ctrl->guest_ctrl.V_INTR_VECTOR,
482 (void *)(addr_t)info->rip);
485 info->intr_core_state.irq_pending = 1;
486 info->intr_core_state.irq_vector = irq;
491 guest_ctrl->EVENTINJ.type = SVM_INJECTION_NMI;
493 case V3_SOFTWARE_INTR:
494 guest_ctrl->EVENTINJ.type = SVM_INJECTION_SOFT_INTR;
496 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
497 PrintDebug("Injecting software interrupt -- type: %d, vector: %d\n",
498 SVM_INJECTION_SOFT_INTR, info->intr_core_state.swintr_vector);
500 guest_ctrl->EVENTINJ.vector = info->intr_core_state.swintr_vector;
501 guest_ctrl->EVENTINJ.valid = 1;
503 /* reset swintr state */
504 info->intr_core_state.swintr_posted = 0;
505 info->intr_core_state.swintr_vector = 0;
509 guest_ctrl->EVENTINJ.type = SVM_INJECTION_IRQ;
512 case V3_INVALID_INTR:
523 v3_svm_config_tsc_virtualization(struct guest_info * info) {
524 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
526 if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
527 ctrl_area->instrs.RDTSC = 1;
528 ctrl_area->svm_instrs.RDTSCP = 1;
530 ctrl_area->instrs.RDTSC = 0;
531 ctrl_area->svm_instrs.RDTSCP = 0;
532 ctrl_area->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
538 * CAUTION and DANGER!!!
540 * The VMCB CANNOT(!!) be accessed outside of the clgi/stgi calls inside this function
541 * When exectuing a symbiotic call, the VMCB WILL be overwritten, so any dependencies
542 * on its contents will cause things to break. The contents at the time of the exit WILL
543 * change before the exit handler is executed.
545 int v3_svm_enter(struct guest_info * info) {
546 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
547 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
548 addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
549 uint64_t guest_cycles = 0;
551 // Conditionally yield the CPU if the timeslice has expired
554 // Update timer devices after being in the VM before doing
555 // IRQ updates, so that any interrupts they raise get seen
557 v3_advance_time(info, NULL);
558 v3_update_timers(info);
560 // disable global interrupts for vm state transition
563 // Synchronize the guest state to the VMCB
564 guest_state->cr0 = info->ctrl_regs.cr0;
565 guest_state->cr2 = info->ctrl_regs.cr2;
566 guest_state->cr3 = info->ctrl_regs.cr3;
567 guest_state->cr4 = info->ctrl_regs.cr4;
568 guest_state->dr6 = info->dbg_regs.dr6;
569 guest_state->dr7 = info->dbg_regs.dr7;
570 guest_ctrl->guest_ctrl.V_TPR = info->ctrl_regs.cr8 & 0xff;
571 guest_state->rflags = info->ctrl_regs.rflags;
572 guest_state->efer = info->ctrl_regs.efer;
574 /* Synchronize MSRs */
575 guest_state->star = info->msrs.star;
576 guest_state->lstar = info->msrs.lstar;
577 guest_state->sfmask = info->msrs.sfmask;
578 guest_state->KernelGsBase = info->msrs.kern_gs_base;
580 guest_state->cpl = info->cpl;
582 v3_set_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
584 guest_state->rax = info->vm_regs.rax;
585 guest_state->rip = info->rip;
586 guest_state->rsp = info->vm_regs.rsp;
588 #ifdef V3_CONFIG_SYMCALL
589 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
590 update_irq_entry_state(info);
593 update_irq_entry_state(info);
600 PrintDebug("SVM Entry to CS=%p rip=%p...\n",
601 (void *)(addr_t)info->segments.cs.base,
602 (void *)(addr_t)info->rip);
605 #ifdef V3_CONFIG_SYMCALL
606 if (info->sym_core_state.symcall_state.sym_call_active == 1) {
607 if (guest_ctrl->guest_ctrl.V_IRQ == 1) {
608 V3_Print("!!! Injecting Interrupt during Sym call !!!\n");
613 v3_svm_config_tsc_virtualization(info);
615 //V3_Print("Calling v3_svm_launch\n");
617 uint64_t entry_tsc = 0;
618 uint64_t exit_tsc = 0;
622 v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[V3_Get_CPU()]);
626 guest_cycles = exit_tsc - entry_tsc;
630 //V3_Print("SVM Returned: Exit Code: %x, guest_rip=%lx\n", (uint32_t)(guest_ctrl->exit_code), (unsigned long)guest_state->rip);
632 v3_last_exit = (uint32_t)(guest_ctrl->exit_code);
634 v3_advance_time(info, &guest_cycles);
638 // Save Guest state from VMCB
639 info->rip = guest_state->rip;
640 info->vm_regs.rsp = guest_state->rsp;
641 info->vm_regs.rax = guest_state->rax;
643 info->cpl = guest_state->cpl;
645 info->ctrl_regs.cr0 = guest_state->cr0;
646 info->ctrl_regs.cr2 = guest_state->cr2;
647 info->ctrl_regs.cr3 = guest_state->cr3;
648 info->ctrl_regs.cr4 = guest_state->cr4;
649 info->dbg_regs.dr6 = guest_state->dr6;
650 info->dbg_regs.dr7 = guest_state->dr7;
651 info->ctrl_regs.cr8 = guest_ctrl->guest_ctrl.V_TPR;
652 info->ctrl_regs.rflags = guest_state->rflags;
653 info->ctrl_regs.efer = guest_state->efer;
655 /* Synchronize MSRs */
656 info->msrs.star = guest_state->star;
657 info->msrs.lstar = guest_state->lstar;
658 info->msrs.sfmask = guest_state->sfmask;
659 info->msrs.kern_gs_base = guest_state->KernelGsBase;
661 v3_get_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
662 info->cpu_mode = v3_get_vm_cpu_mode(info);
663 info->mem_mode = v3_get_vm_mem_mode(info);
666 // save exit info here
667 exit_code = guest_ctrl->exit_code;
668 exit_info1 = guest_ctrl->exit_info1;
669 exit_info2 = guest_ctrl->exit_info2;
671 #ifdef V3_CONFIG_SYMCALL
672 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
673 update_irq_exit_state(info);
676 update_irq_exit_state(info);
679 // reenable global interrupts after vm exit
682 // Conditionally yield the CPU if the timeslice has expired
685 // This update timers is for time-dependent handlers
686 // if we're slaved to host time
687 v3_advance_time(info, NULL);
688 v3_update_timers(info);
691 int ret = v3_handle_svm_exit(info, exit_code, exit_info1, exit_info2);
694 PrintError("Error in SVM exit handler (ret=%d)\n", ret);
695 PrintError(" last Exit was %d (exit code=0x%llx)\n", v3_last_exit, (uint64_t) exit_code);
700 if (info->timeouts.timeout_active) {
701 /* Check to see if any timeouts have expired */
702 v3_handle_timeouts(info, guest_cycles);
710 int v3_start_svm_guest(struct guest_info * info) {
711 // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
712 // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
714 PrintDebug("Starting SVM core %u (on logical core %u)\n", info->vcpu_id, info->pcpu_id);
716 if (info->vcpu_id == 0) {
717 info->core_run_state = CORE_RUNNING;
719 PrintDebug("SVM core %u (on %u): Waiting for core initialization\n", info->vcpu_id, info->pcpu_id);
721 while (info->core_run_state == CORE_STOPPED) {
723 if (info->vm_info->run_state == VM_STOPPED) {
724 // The VM was stopped before this core was initialized.
729 //PrintDebug("SVM core %u: still waiting for INIT\n", info->vcpu_id);
732 PrintDebug("SVM core %u(on %u) initialized\n", info->vcpu_id, info->pcpu_id);
734 // We'll be paranoid about race conditions here
735 v3_wait_at_barrier(info);
738 PrintDebug("SVM core %u(on %u): I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
739 info->vcpu_id, info->pcpu_id,
740 info->segments.cs.selector, (void *)(info->segments.cs.base),
741 info->segments.cs.limit, (void *)(info->rip));
745 PrintDebug("SVM core %u: Launching SVM VM (vmcb=%p) (on cpu %u)\n",
746 info->vcpu_id, (void *)info->vmm_data, info->pcpu_id);
747 //PrintDebugVMCB((vmcb_t*)(info->vmm_data));
753 if (info->vm_info->run_state == VM_STOPPED) {
754 info->core_run_state = CORE_STOPPED;
758 if (v3_svm_enter(info) == -1) {
759 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
761 addr_t linear_addr = 0;
763 info->vm_info->run_state = VM_ERROR;
765 V3_Print("SVM core %u: SVM ERROR!!\n", info->vcpu_id);
767 v3_print_guest_state(info);
769 V3_Print("SVM core %u: SVM Exit Code: %p\n", info->vcpu_id, (void *)(addr_t)guest_ctrl->exit_code);
771 V3_Print("SVM core %u: exit_info1 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info1));
772 V3_Print("SVM core %u: exit_info1 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
774 V3_Print("SVM core %u: exit_info2 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info2));
775 V3_Print("SVM core %u: exit_info2 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
777 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
779 if (info->mem_mode == PHYSICAL_MEM) {
780 v3_gpa_to_hva(info, linear_addr, &host_addr);
781 } else if (info->mem_mode == VIRTUAL_MEM) {
782 v3_gva_to_hva(info, linear_addr, &host_addr);
785 V3_Print("SVM core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
787 V3_Print("SVM core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
788 v3_dump_mem((uint8_t *)host_addr, 15);
790 v3_print_stack(info);
795 v3_wait_at_barrier(info);
798 if (info->vm_info->run_state == VM_STOPPED) {
799 info->core_run_state = CORE_STOPPED;
806 if ((info->num_exits % 50000) == 0) {
807 V3_Print("SVM Exit number %d\n", (uint32_t)info->num_exits);
808 v3_print_guest_state(info);
814 // Need to take down the other cores on error...
822 int v3_reset_svm_vm_core(struct guest_info * core, addr_t rip) {
825 // Write the RIP, CS, and descriptor
826 // assume the rest is already good to go
828 // vector VV -> rip at 0
830 // This means we start executing at linear address VV000
832 // So the selector needs to be VV00
833 // and the base needs to be VV000
836 core->segments.cs.selector = rip << 8;
837 core->segments.cs.limit = 0xffff;
838 core->segments.cs.base = rip << 12;
848 /* Checks machine SVM capability */
849 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
850 int v3_is_svm_capable() {
851 uint_t vm_cr_low = 0, vm_cr_high = 0;
852 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
854 v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
856 PrintDebug("CPUID_EXT_FEATURE_IDS_ecx=0x%x\n", ecx);
858 if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
859 V3_Print("SVM Not Available\n");
862 v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
864 PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
866 if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
867 V3_Print("SVM is available but is disabled.\n");
869 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
871 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
873 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
874 V3_Print("SVM BIOS Disabled, not unlockable\n");
876 V3_Print("SVM is locked with a key\n");
881 V3_Print("SVM is available and enabled.\n");
883 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
884 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_eax=0x%x\n", eax);
885 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ebx=0x%x\n", ebx);
886 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ecx=0x%x\n", ecx);
887 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
894 static int has_svm_nested_paging() {
895 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
897 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
899 //PrintDebug("CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
901 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
902 V3_Print("SVM Nested Paging not supported\n");
905 V3_Print("SVM Nested Paging supported\n");
912 void v3_init_svm_cpu(int cpu_id) {
914 extern v3_cpu_arch_t v3_cpu_types[];
916 // Enable SVM on the CPU
917 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
918 msr.e_reg.low |= EFER_MSR_svm_enable;
919 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
921 V3_Print("SVM Enabled\n");
923 // Setup the host state save area
924 host_vmcbs[cpu_id] = (addr_t)V3_AllocPages(4);
927 // msr.e_reg.high = 0;
928 //msr.e_reg.low = (uint_t)host_vmcb;
929 msr.r_reg = host_vmcbs[cpu_id];
931 PrintDebug("Host State being saved at %p\n", (void *)host_vmcbs[cpu_id]);
932 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
935 if (has_svm_nested_paging() == 1) {
936 v3_cpu_types[cpu_id] = V3_SVM_REV3_CPU;
938 v3_cpu_types[cpu_id] = V3_SVM_CPU;
944 void v3_deinit_svm_cpu(int cpu_id) {
946 extern v3_cpu_arch_t v3_cpu_types[];
948 // reset SVM_VM_HSAVE_PA_MSR
949 // Does setting it to NULL disable??
951 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
954 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
955 msr.e_reg.low &= ~EFER_MSR_svm_enable;
956 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
958 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
960 V3_FreePages((void *)host_vmcbs[cpu_id], 4);
962 V3_Print("Host CPU %d host area freed, and SVM disabled\n", cpu_id);
1017 * Test VMSAVE/VMLOAD Latency
1019 #define vmsave ".byte 0x0F,0x01,0xDB ; "
1020 #define vmload ".byte 0x0F,0x01,0xDA ; "
1022 uint32_t start_lo, start_hi;
1023 uint32_t end_lo, end_hi;
1024 uint64_t start, end;
1026 __asm__ __volatile__ (
1028 "movl %%eax, %%esi ; "
1029 "movl %%edx, %%edi ; "
1030 "movq %%rcx, %%rax ; "
1033 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1034 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1045 PrintDebug("VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
1047 __asm__ __volatile__ (
1049 "movl %%eax, %%esi ; "
1050 "movl %%edx, %%edi ; "
1051 "movq %%rcx, %%rax ; "
1054 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1055 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1067 PrintDebug("VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
1069 /* End Latency Test */
1080 void Init_VMCB_pe(vmcb_t *vmcb, struct guest_info vm_info) {
1081 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
1082 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
1086 guest_state->rsp = vm_info.vm_regs.rsp;
1087 guest_state->rip = vm_info.rip;
1090 /* I pretty much just gutted this from TVMM */
1091 /* Note: That means its probably wrong */
1093 // set the segment registers to mirror ours
1094 guest_state->cs.selector = 1<<3;
1095 guest_state->cs.attrib.fields.type = 0xa; // Code segment+read
1096 guest_state->cs.attrib.fields.S = 1;
1097 guest_state->cs.attrib.fields.P = 1;
1098 guest_state->cs.attrib.fields.db = 1;
1099 guest_state->cs.attrib.fields.G = 1;
1100 guest_state->cs.limit = 0xfffff;
1101 guest_state->cs.base = 0;
1103 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
1104 for ( i = 0; segregs[i] != NULL; i++) {
1105 struct vmcb_selector * seg = segregs[i];
1107 seg->selector = 2<<3;
1108 seg->attrib.fields.type = 0x2; // Data Segment+read/write
1109 seg->attrib.fields.S = 1;
1110 seg->attrib.fields.P = 1;
1111 seg->attrib.fields.db = 1;
1112 seg->attrib.fields.G = 1;
1113 seg->limit = 0xfffff;
1119 /* JRL THIS HAS TO GO */
1121 // guest_state->tr.selector = GetTR_Selector();
1122 guest_state->tr.attrib.fields.type = 0x9;
1123 guest_state->tr.attrib.fields.P = 1;
1124 // guest_state->tr.limit = GetTR_Limit();
1125 //guest_state->tr.base = GetTR_Base();// - 0x2000;
1133 guest_state->efer |= EFER_MSR_svm_enable;
1134 guest_state->rflags = 0x00000002; // The reserved bit is always 1
1135 ctrl_area->svm_instrs.VMRUN = 1;
1136 guest_state->cr0 = 0x00000001; // PE
1137 ctrl_area->guest_ASID = 1;
1140 // guest_state->cpl = 0;
1146 ctrl_area->cr_writes.cr4 = 1;
1148 ctrl_area->exceptions.de = 1;
1149 ctrl_area->exceptions.df = 1;
1150 ctrl_area->exceptions.pf = 1;
1151 ctrl_area->exceptions.ts = 1;
1152 ctrl_area->exceptions.ss = 1;
1153 ctrl_area->exceptions.ac = 1;
1154 ctrl_area->exceptions.mc = 1;
1155 ctrl_area->exceptions.gp = 1;
1156 ctrl_area->exceptions.ud = 1;
1157 ctrl_area->exceptions.np = 1;
1158 ctrl_area->exceptions.of = 1;
1159 ctrl_area->exceptions.nmi = 1;
1163 ctrl_area->instrs.IOIO_PROT = 1;
1164 ctrl_area->IOPM_BASE_PA = (uint_t)V3_AllocPages(3);
1168 tmp_reg.r_reg = ctrl_area->IOPM_BASE_PA;
1169 memset((void*)(tmp_reg.e_reg.low), 0xffffffff, PAGE_SIZE * 2);
1172 ctrl_area->instrs.INTR = 1;
1179 memset(gdt_buf, 0, 6);
1180 memset(idt_buf, 0, 6);
1183 uint_t gdt_base, idt_base;
1184 ushort_t gdt_limit, idt_limit;
1187 gdt_base = *(ulong_t*)((uchar_t*)gdt_buf + 2) & 0xffffffff;
1188 gdt_limit = *(ushort_t*)(gdt_buf) & 0xffff;
1189 PrintDebug("GDT: base: %x, limit: %x\n", gdt_base, gdt_limit);
1192 idt_base = *(ulong_t*)(idt_buf + 2) & 0xffffffff;
1193 idt_limit = *(ushort_t*)(idt_buf) & 0xffff;
1194 PrintDebug("IDT: base: %x, limit: %x\n",idt_base, idt_limit);
1197 // gdt_base -= 0x2000;
1198 //idt_base -= 0x2000;
1200 guest_state->gdtr.base = gdt_base;
1201 guest_state->gdtr.limit = gdt_limit;
1202 guest_state->idtr.base = idt_base;
1203 guest_state->idtr.limit = idt_limit;
1209 // also determine if CPU supports nested paging
1211 if (vm_info.page_tables) {
1213 // Flush the TLB on entries/exits
1214 ctrl_area->TLB_CONTROL = 1;
1216 // Enable Nested Paging
1217 ctrl_area->NP_ENABLE = 1;
1219 PrintDebug("NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
1221 // Set the Nested Page Table pointer
1222 ctrl_area->N_CR3 |= ((addr_t)vm_info.page_tables & 0xfffff000);
1225 // ctrl_area->N_CR3 = Get_CR3();
1226 // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
1228 guest_state->g_pat = 0x7040600070406ULL;
1230 PrintDebug("Set Nested CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(ctrl_area->N_CR3)), (uint_t)*((unsigned char *)&(ctrl_area->N_CR3) + 4));
1231 PrintDebug("Set Guest CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(guest_state->cr3)), (uint_t)*((unsigned char *)&(guest_state->cr3) + 4));
1233 // guest_state->cr0 |= 0x80000000;