2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
15 * Peter Dinda <jarusl@cs.northwestern.edu> (Reset)
17 * This is free software. You are permitted to use,
18 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
23 #include <palacios/svm.h>
24 #include <palacios/vmm.h>
26 #include <palacios/vmcb.h>
27 #include <palacios/vmm_mem.h>
28 #include <palacios/vmm_paging.h>
29 #include <palacios/svm_handler.h>
31 #include <palacios/vmm_debug.h>
32 #include <palacios/vm_guest_mem.h>
34 #include <palacios/vmm_decoder.h>
35 #include <palacios/vmm_string.h>
36 #include <palacios/vmm_lowlevel.h>
37 #include <palacios/svm_msr.h>
39 #include <palacios/vmm_rbtree.h>
40 #include <palacios/vmm_barrier.h>
41 #include <palacios/vmm_debug.h>
43 #include <palacios/vmm_perftune.h>
45 #include <palacios/vmm_bios.h>
48 #ifdef V3_CONFIG_CHECKPOINT
49 #include <palacios/vmm_checkpoint.h>
52 #include <palacios/vmm_direct_paging.h>
54 #include <palacios/vmm_ctrl_regs.h>
55 #include <palacios/svm_io.h>
57 #include <palacios/vmm_sprintf.h>
59 #ifdef V3_CONFIG_MEM_TRACK
60 #include <palacios/vmm_mem_track.h>
63 #ifdef V3_CONFIG_TM_FUNC
64 #include <extensions/trans_mem.h>
67 #ifndef V3_CONFIG_DEBUG_SVM
69 #define PrintDebug(fmt, args...)
74 uint32_t v3_last_exit;
76 // This is a global pointer to the host's VMCB
77 // These are physical addresses
78 static addr_t host_vmcbs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
82 extern void v3_stgi();
83 extern void v3_clgi();
84 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
85 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
89 static vmcb_t * Allocate_VMCB() {
90 vmcb_t * vmcb_page = NULL;
91 addr_t vmcb_pa = (addr_t)V3_AllocPages(1); // need not be shadow safe, not exposed to guest
93 if ((void *)vmcb_pa == NULL) {
94 PrintError(VM_NONE, VCORE_NONE, "Error allocating VMCB\n");
98 vmcb_page = (vmcb_t *)V3_VAddr((void *)vmcb_pa);
100 memset(vmcb_page, 0, 4096);
106 static int v3_svm_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data)
110 // Call arch-independent handler
111 if ((status = v3_handle_efer_write(core, msr, src, priv_data)) != 0) {
117 // Ensure that hardware visible EFER.SVME bit is set (SVM Enable)
118 struct efer_64 * hw_efer = (struct efer_64 *)&(core->ctrl_regs.efer);
126 * This is invoked both on an initial boot and on a reset
128 * The difference is that on a reset we will not rehook anything
132 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info * core) {
133 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
134 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
137 if (core->core_run_state!=CORE_INVALID && core->core_run_state!=CORE_RESETTING) {
138 PrintError(core->vm_info, core, "Atempt to Init_VMCB_BIOS in invalid state (%d)\n",core->core_run_state);
142 // need to invalidate any shadow page tables early
143 if (core->shdw_pg_mode == SHADOW_PAGING && core->core_run_state==CORE_RESETTING) {
144 if (v3_get_vm_cpu_mode(core) != REAL) {
145 if (v3_invalidate_shadow_pts(core) == -1) {
146 PrintError(core->vm_info,core,"Could not invalidate shadow page tables\n");
152 // Guarantee we are starting from a clean slate
156 ctrl_area->svm_instrs.VMRUN = 1;
157 ctrl_area->svm_instrs.VMMCALL = 1;
158 ctrl_area->svm_instrs.VMLOAD = 1;
159 ctrl_area->svm_instrs.VMSAVE = 1;
160 ctrl_area->svm_instrs.STGI = 1;
161 ctrl_area->svm_instrs.CLGI = 1;
162 ctrl_area->svm_instrs.SKINIT = 1; // secure startup... why
163 ctrl_area->svm_instrs.ICEBP = 1; // in circuit emulator breakpoint
164 ctrl_area->svm_instrs.WBINVD = 1; // write back and invalidate caches... why?
165 ctrl_area->svm_instrs.MONITOR = 1;
166 ctrl_area->svm_instrs.MWAIT_always = 1;
167 ctrl_area->svm_instrs.MWAIT_if_armed = 1;
168 ctrl_area->instrs.INVLPGA = 1; // invalidate page in asid... why?
169 ctrl_area->instrs.CPUID = 1;
171 ctrl_area->instrs.HLT = 1;
173 /* Set at VMM launch as needed */
174 ctrl_area->instrs.RDTSC = 0;
175 ctrl_area->svm_instrs.RDTSCP = 0;
178 #ifdef V3_CONFIG_TM_FUNC
179 v3_tm_set_excp_intercepts(ctrl_area);
183 ctrl_area->instrs.NMI = 1;
184 ctrl_area->instrs.SMI = 0; // allow SMIs to run in guest
185 ctrl_area->instrs.INIT = 1;
186 // ctrl_area->instrs.PAUSE = 1; // do not care as does not halt
187 ctrl_area->instrs.shutdown_evts = 1;
190 /* DEBUG FOR RETURN CODE */
191 ctrl_area->exit_code = 1;
194 /* Setup Guest Machine state */
196 memset(&core->vm_regs,0,sizeof(core->vm_regs));
197 memset(&core->ctrl_regs,0,sizeof(core->ctrl_regs));
198 memset(&core->dbg_regs,0,sizeof(core->dbg_regs));
199 memset(&core->segments,0,sizeof(core->segments));
200 memset(&core->msrs,0,sizeof(core->msrs));
201 memset(&core->fp_state,0,sizeof(core->fp_state));
204 core->intr_core_state.irq_pending=0;
205 core->intr_core_state.irq_started=0;
206 core->intr_core_state.swintr_posted=0;
209 core->excp_state.excp_pending=0;
211 // reset of gprs to expected values at init
212 core->vm_regs.rsp = 0x00;
214 core->vm_regs.rdx = 0x00000f00; // family/stepping/etc
219 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
221 core->ctrl_regs.cr0 = 0x60010010; // Set the WP flag so the memory hooks work in real-mode
222 core->shdw_pg_state.guest_cr0 = core->ctrl_regs.cr0;
225 core->shdw_pg_state.guest_cr3 = core->ctrl_regs.cr3;
227 core->shdw_pg_state.guest_cr4 = core->ctrl_regs.cr4;
229 core->ctrl_regs.efer |= EFER_MSR_svm_enable ;
230 core->shdw_pg_state.guest_efer.value = core->ctrl_regs.efer;
232 core->segments.cs.selector = 0xf000;
233 core->segments.cs.limit = 0xffff;
234 core->segments.cs.base = 0x0000f0000LL;
236 // (raw attributes = 0xf3)
237 core->segments.cs.type = 0xa;
238 core->segments.cs.system = 0x1;
239 core->segments.cs.dpl = 0x0;
240 core->segments.cs.present = 1;
244 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
245 &(core->segments.es), &(core->segments.fs),
246 &(core->segments.gs), NULL};
248 for ( i = 0; segregs[i] != NULL; i++) {
249 struct v3_segment * seg = segregs[i];
251 seg->selector = 0x0000;
252 // seg->base = seg->selector << 4;
253 seg->base = 0x00000000;
256 // (raw attributes = 0xf3)
263 core->segments.gdtr.selector = 0x0000;
264 core->segments.gdtr.limit = 0x0000ffff;
265 core->segments.gdtr.base = 0x0000000000000000LL;
266 core->segments.gdtr.dpl = 0x0;
268 core->segments.idtr.selector = 0x0000;
269 core->segments.idtr.limit = 0x0000ffff;
270 core->segments.idtr.base = 0x0000000000000000LL;
271 core->segments.ldtr.limit = 0x0000ffff;
272 core->segments.ldtr.base = 0x0000000000000000LL;
273 core->segments.ldtr.system = 0;
274 core->segments.ldtr.type = 0x2;
275 core->segments.ldtr.dpl = 0x0;
277 core->segments.tr.selector = 0x0000;
278 core->segments.tr.limit = 0x0000ffff;
279 core->segments.tr.base = 0x0000000000000000LL;
280 core->segments.tr.system = 0;
281 core->segments.tr.type = 0x3;
282 core->segments.tr.dpl = 0x0;
284 core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
285 core->dbg_regs.dr7 = 0x0000000000000400LL;
288 ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->io_map.arch_data);
289 ctrl_area->instrs.IOIO_PROT = 1;
291 ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data);
292 ctrl_area->instrs.MSR_PROT = 1;
295 ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
296 ctrl_area->instrs.INTR = 1;
297 // The above also assures the TPR changes (CR8) are only virtual
300 // However, we need to see TPR writes since they will
301 // affect the virtual apic
302 // we reflect out cr8 to ctrl_regs->apic_tpr
303 ctrl_area->cr_reads.cr8 = 1;
304 ctrl_area->cr_writes.cr8 = 1;
305 // We will do all TPR comparisons in the virtual apic
306 // We also do not want the V_TPR to be able to mask the PIC
307 ctrl_area->guest_ctrl.V_IGN_TPR = 1;
311 if (core->core_run_state == CORE_INVALID) {
312 v3_hook_msr(core->vm_info, EFER_MSR,
313 &v3_handle_efer_read,
314 &v3_svm_handle_efer_write,
318 if (core->shdw_pg_mode == SHADOW_PAGING) {
320 /* JRL: This is a performance killer, and a simplistic solution */
321 /* We need to fix this */
322 ctrl_area->TLB_CONTROL = 1;
323 ctrl_area->guest_ASID = 1;
326 if (core->core_run_state == CORE_INVALID) {
327 if (v3_init_passthrough_pts(core) == -1) {
328 PrintError(core->vm_info, core, "Could not initialize passthrough page tables\n");
331 // the shadow page tables are OK since we have not initialized hem yet
334 // invalidation of shadow page tables happened earlier in this function
337 core->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
339 core->ctrl_regs.cr0 |= 0x80000000;
341 v3_activate_passthrough_pt(core);
343 ctrl_area->cr_reads.cr0 = 1;
344 ctrl_area->cr_writes.cr0 = 1;
345 //intercept cr4 read so shadow pager can use PAE independently of guest
346 ctrl_area->cr_reads.cr4 = 1;
347 ctrl_area->cr_writes.cr4 = 1;
348 ctrl_area->cr_reads.cr3 = 1;
349 ctrl_area->cr_writes.cr3 = 1;
352 ctrl_area->instrs.INVLPG = 1;
354 ctrl_area->exceptions.pf = 1;
356 guest_state->g_pat = 0x7040600070406ULL;
359 } else if (core->shdw_pg_mode == NESTED_PAGING) {
360 // Flush the TLB on entries/exits
361 ctrl_area->TLB_CONTROL = 1;
362 ctrl_area->guest_ASID = 1;
364 // Enable Nested Paging
365 ctrl_area->NP_ENABLE = 1;
367 PrintDebug(core->vm_info, core, "NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
369 // Set the Nested Page Table pointer
370 if (core->core_run_state == CORE_INVALID) {
371 if (v3_init_passthrough_pts(core) == -1) {
372 PrintError(core->vm_info, core, "Could not initialize Nested page tables\n");
376 // the existing nested page tables will work fine
379 ctrl_area->N_CR3 = core->direct_map_pt;
381 guest_state->g_pat = 0x7040600070406ULL;
384 /* tell the guest that we don't support SVM */
385 if (core->core_run_state == CORE_INVALID) {
386 v3_hook_msr(core->vm_info, SVM_VM_CR_MSR,
387 &v3_handle_vm_cr_read,
388 &v3_handle_vm_cr_write,
392 if (core->core_run_state == CORE_INVALID) {
393 #define INT_PENDING_AMD_MSR 0xc0010055
395 v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
396 v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
397 v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
398 v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
399 v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
401 v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
402 v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
403 v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
406 v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
407 v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
409 // Passthrough read operations are ok.
410 v3_hook_msr(core->vm_info, INT_PENDING_AMD_MSR, NULL, v3_msr_unhandled_write, NULL);
417 int v3_init_svm_vmcb(struct guest_info * core, v3_vm_class_t vm_class) {
419 PrintDebug(core->vm_info, core, "Allocating VMCB\n");
420 core->vmm_data = (void *)Allocate_VMCB();
422 if (core->vmm_data == NULL) {
423 PrintError(core->vm_info, core, "Could not allocate VMCB, Exiting...\n");
427 if (vm_class == V3_PC_VM) {
428 PrintDebug(core->vm_info, core, "Initializing VMCB (addr=%p)\n", (void *)core->vmm_data);
429 Init_VMCB_BIOS((vmcb_t*)(core->vmm_data), core);
431 PrintError(core->vm_info, core, "Invalid VM class\n");
435 core->core_run_state = CORE_STOPPED;
441 int v3_deinit_svm_vmcb(struct guest_info * core) {
442 if (core->vmm_data) {
443 V3_FreePages(V3_PAddr(core->vmm_data), 1);
449 static int svm_handle_standard_reset(struct guest_info *core)
451 if (core->core_run_state != CORE_RESETTING) {
455 PrintDebug(core->vm_info,core,"Handling standard reset (guest state before follows)\n");
457 #ifdef V3_CONFIG_DEBUG_SVM
458 v3_print_guest_state(core);
461 // wait until all resetting cores get here (ROS or whole VM)
462 v3_counting_barrier(&core->vm_info->reset_barrier);
464 // I could be a ROS core, or I could be in a non-HVM
465 // either way, if I'm core 0, I'm the leader
466 if (core->vcpu_id==0) {
467 uint64_t mem_size=core->vm_info->mem_size;
470 // on a ROS reset, we should only
471 // manipulate the part of the memory seen by
473 if (core->vm_info->hvm_state.is_hvm) {
474 mem_size=v3_get_hvm_ros_memsize(core->vm_info);
477 core->vm_info->run_state = VM_RESETTING;
478 // copy bioses again because some,
479 // like seabios, assume
480 // this should also blow away the BDA and EBDA
481 PrintDebug(core->vm_info,core,"Clear memory (%p bytes)\n",(void*)core->vm_info->mem_size);
482 if (v3_set_gpa_memory(core, 0, mem_size, 0)!=mem_size) {
483 PrintError(core->vm_info,core,"Clear of memory failed\n");
485 PrintDebug(core->vm_info,core,"Copying bioses\n");
486 if (v3_setup_bioses(core->vm_info, core->vm_info->cfg_data->cfg)) {
487 PrintError(core->vm_info,core,"Setup of bioses failed\n");
491 Init_VMCB_BIOS((vmcb_t*)(core->vmm_data), core);
493 PrintDebug(core->vm_info,core,"InitVMCB done\n");
496 core->cpu_mode = REAL;
497 core->mem_mode = PHYSICAL_MEM;
500 PrintDebug(core->vm_info,core,"Machine reset to REAL/PHYSICAL\n");
502 memset(V3_VAddr((void*)(host_vmcbs[V3_Get_CPU()])),0,4096*4); // good measure...
504 // core zero will be restarted by the main execution loop
505 core->core_run_state = CORE_STOPPED;
507 if (core->vcpu_id==0) {
508 core->vm_info->run_state = VM_RUNNING;
511 #ifdef V3_CONFIG_DEBUG_SVM
512 PrintDebug(core->vm_info,core,"VMCB state at end of reset\n");
513 PrintDebugVMCB((vmcb_t*)(core->vmm_data));
514 PrintDebug(core->vm_info,core,"Guest state at end of reset\n");
515 v3_print_guest_state(core);
518 // wait until we are all ready to go
519 v3_counting_barrier(&core->vm_info->reset_barrier);
521 PrintDebug(core->vm_info,core,"Returning with request for recycle loop\n");
523 return 1; // reboot is occuring
527 #ifdef V3_CONFIG_CHECKPOINT
528 int v3_svm_save_core(struct guest_info * core, void * ctx){
530 vmcb_saved_state_t * guest_area = GET_VMCB_SAVE_STATE_AREA(core->vmm_data);
532 // Special case saves of data we need immediate access to
534 V3_CHKPT_SAVE(ctx, "CPL", core->cpl, failout);
535 V3_CHKPT_SAVE(ctx,"STAR", guest_area->star, failout);
536 V3_CHKPT_SAVE(ctx,"CSTAR", guest_area->cstar, failout);
537 V3_CHKPT_SAVE(ctx,"LSTAR", guest_area->lstar, failout);
538 V3_CHKPT_SAVE(ctx,"SFMASK", guest_area->sfmask, failout);
539 V3_CHKPT_SAVE(ctx,"KERNELGSBASE", guest_area->KernelGsBase, failout);
540 V3_CHKPT_SAVE(ctx,"SYSENTER_CS", guest_area->sysenter_cs, failout);
541 V3_CHKPT_SAVE(ctx,"SYSENTER_ESP", guest_area->sysenter_esp, failout);
542 V3_CHKPT_SAVE(ctx,"SYSENTER_EIP", guest_area->sysenter_eip, failout);
544 // and then we save the whole enchilada
545 if (v3_chkpt_save(ctx, "VMCB_DATA", PAGE_SIZE, core->vmm_data)) {
546 PrintError(core->vm_info, core, "Could not save SVM vmcb\n");
553 PrintError(core->vm_info, core, "Failed to save SVM state for core\n");
558 int v3_svm_load_core(struct guest_info * core, void * ctx){
561 vmcb_saved_state_t * guest_area = GET_VMCB_SAVE_STATE_AREA(core->vmm_data);
563 // Reload what we special cased, which we will overwrite in a minute
564 V3_CHKPT_LOAD(ctx, "CPL", core->cpl, failout);
565 V3_CHKPT_LOAD(ctx,"STAR", guest_area->star, failout);
566 V3_CHKPT_LOAD(ctx,"CSTAR", guest_area->cstar, failout);
567 V3_CHKPT_LOAD(ctx,"LSTAR", guest_area->lstar, failout);
568 V3_CHKPT_LOAD(ctx,"SFMASK", guest_area->sfmask, failout);
569 V3_CHKPT_LOAD(ctx,"KERNELGSBASE", guest_area->KernelGsBase, failout);
570 V3_CHKPT_LOAD(ctx,"SYSENTER_CS", guest_area->sysenter_cs, failout);
571 V3_CHKPT_LOAD(ctx,"SYSENTER_ESP", guest_area->sysenter_esp, failout);
572 V3_CHKPT_LOAD(ctx,"SYSENTER_EIP", guest_area->sysenter_eip, failout);
574 // and then we load the whole enchilada
575 if (v3_chkpt_load(ctx, "VMCB_DATA", PAGE_SIZE, core->vmm_data)) {
576 PrintError(core->vm_info, core, "Could not load SVM vmcb\n");
583 PrintError(core->vm_info, core, "Failed to save SVM state for core\n");
589 static int update_irq_exit_state(struct guest_info * info) {
590 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
592 // Fix for QEMU bug using EVENTINJ as an internal cache
593 guest_ctrl->EVENTINJ.valid = 0;
595 if ((info->intr_core_state.irq_pending == 1) && (guest_ctrl->guest_ctrl.V_IRQ == 0)) {
597 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
598 PrintDebug(info->vm_info, info, "INTAK cycle completed for irq %d\n", info->intr_core_state.irq_vector);
601 info->intr_core_state.irq_started = 1;
602 info->intr_core_state.irq_pending = 0;
604 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
607 if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 0)) {
608 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
609 PrintDebug(info->vm_info, info, "Interrupt %d taken by guest\n", info->intr_core_state.irq_vector);
612 // Interrupt was taken fully vectored
613 info->intr_core_state.irq_started = 0;
615 } else if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 1)) {
616 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
617 PrintDebug(info->vm_info, info, "EXIT INT INFO is set (vec=%d)\n", guest_ctrl->exit_int_info.vector);
625 static int update_irq_entry_state(struct guest_info * info) {
626 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
629 if (info->intr_core_state.irq_pending == 0) {
630 guest_ctrl->guest_ctrl.V_IRQ = 0;
631 guest_ctrl->guest_ctrl.V_INTR_VECTOR = 0;
634 if (v3_excp_pending(info)) {
635 uint_t excp = v3_get_excp_number(info);
637 guest_ctrl->EVENTINJ.type = SVM_INJECTION_EXCEPTION;
639 if (info->excp_state.excp_error_code_valid) {
640 guest_ctrl->EVENTINJ.error_code = info->excp_state.excp_error_code;
641 guest_ctrl->EVENTINJ.ev = 1;
642 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
643 PrintDebug(info->vm_info, info, "Injecting exception %d with error code %x\n", excp, guest_ctrl->EVENTINJ.error_code);
647 guest_ctrl->EVENTINJ.vector = excp;
649 guest_ctrl->EVENTINJ.valid = 1;
651 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
652 PrintDebug(info->vm_info, info, "<%d> Injecting Exception %d (CR2=%p) (EIP=%p)\n",
653 (int)info->num_exits,
654 guest_ctrl->EVENTINJ.vector,
655 (void *)(addr_t)info->ctrl_regs.cr2,
656 (void *)(addr_t)info->rip);
659 v3_injecting_excp(info, excp);
660 } else if (info->intr_core_state.irq_started == 1) {
661 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
662 PrintDebug(info->vm_info, info, "IRQ pending from previous injection\n");
664 guest_ctrl->guest_ctrl.V_IRQ = 1;
665 guest_ctrl->guest_ctrl.V_INTR_VECTOR = info->intr_core_state.irq_vector;
667 // We ignore the virtual TPR on this injection
668 // TPR/PPR tests have already been done in the APIC.
669 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
670 guest_ctrl->guest_ctrl.V_INTR_PRIO = info->intr_core_state.irq_vector >> 4 ; // 0xf;
673 switch (v3_intr_pending(info)) {
674 case V3_EXTERNAL_IRQ: {
675 int irq = v3_get_intr(info);
681 guest_ctrl->guest_ctrl.V_IRQ = 1;
682 guest_ctrl->guest_ctrl.V_INTR_VECTOR = irq;
684 // We ignore the virtual TPR on this injection
685 // TPR/PPR tests have already been done in the APIC.
686 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
687 guest_ctrl->guest_ctrl.V_INTR_PRIO = info->intr_core_state.irq_vector >> 4 ; // 0xf;
689 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
690 PrintDebug(info->vm_info, info, "Injecting Interrupt %d (EIP=%p)\n",
691 guest_ctrl->guest_ctrl.V_INTR_VECTOR,
692 (void *)(addr_t)info->rip);
695 info->intr_core_state.irq_pending = 1;
696 info->intr_core_state.irq_vector = irq;
702 guest_ctrl->EVENTINJ.type = SVM_INJECTION_NMI;
704 case V3_SOFTWARE_INTR:
705 guest_ctrl->EVENTINJ.type = SVM_INJECTION_SOFT_INTR;
706 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
707 PrintDebug(info->vm_info, info, "Injecting software interrupt -- type: %d, vector: %d\n",
708 SVM_INJECTION_SOFT_INTR, info->intr_core_state.swintr_vector);
710 guest_ctrl->EVENTINJ.vector = info->intr_core_state.swintr_vector;
711 guest_ctrl->EVENTINJ.valid = 1;
713 /* reset swintr state */
714 info->intr_core_state.swintr_posted = 0;
715 info->intr_core_state.swintr_vector = 0;
718 guest_ctrl->EVENTINJ.type = SVM_INJECTION_IRQ;
721 case V3_INVALID_INTR:
732 v3_svm_config_tsc_virtualization(struct guest_info * info) {
733 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
736 if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
737 ctrl_area->instrs.RDTSC = 1;
738 ctrl_area->svm_instrs.RDTSCP = 1;
740 ctrl_area->instrs.RDTSC = 0;
741 ctrl_area->svm_instrs.RDTSCP = 0;
743 if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) {
744 ctrl_area->TSC_OFFSET = 0;
746 ctrl_area->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
755 * CAUTION and DANGER!!!
757 * The VMCB CANNOT(!!) be accessed outside of the clgi/stgi calls inside this function
758 * When exectuing a symbiotic call, the VMCB WILL be overwritten, so any dependencies
759 * on its contents will cause things to break. The contents at the time of the exit WILL
760 * change before the exit handler is executed.
762 int v3_svm_enter(struct guest_info * info) {
763 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
764 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
765 addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
766 uint64_t guest_cycles = 0;
769 // Conditionally yield the CPU if the timeslice has expired
772 #ifdef V3_CONFIG_MEM_TRACK
773 v3_mem_track_entry(info);
776 // Update timer devices after being in the VM before doing
777 // IRQ updates, so that any interrupts they raise get seen
780 v3_advance_time(info, NULL);
782 v3_update_timers(info);
785 // disable global interrupts for vm state transition
788 // Synchronize the guest state to the VMCB
789 guest_state->cr0 = info->ctrl_regs.cr0;
790 guest_state->cr2 = info->ctrl_regs.cr2;
791 guest_state->cr3 = info->ctrl_regs.cr3;
792 guest_state->cr4 = info->ctrl_regs.cr4;
793 guest_state->dr6 = info->dbg_regs.dr6;
794 guest_state->dr7 = info->dbg_regs.dr7;
796 // CR8 is now updated by read/writes and it contains the APIC TPR
797 // the V_TPR should be just the class part of that.
798 // This update is here just for completeness. We currently
799 // are ignoring V_TPR on all injections and doing the priority logivc
801 // guest_ctrl->guest_ctrl.V_TPR = ((info->ctrl_regs.apic_tpr) >> 4) & 0xf;
803 //guest_ctrl->guest_ctrl.V_TPR = info->ctrl_regs.cr8 & 0xff;
806 guest_state->rflags = info->ctrl_regs.rflags;
810 guest_state->efer = info->ctrl_regs.efer;
812 /* Synchronize MSRs */
813 guest_state->star = info->msrs.star;
814 guest_state->lstar = info->msrs.lstar;
815 guest_state->sfmask = info->msrs.sfmask;
816 guest_state->KernelGsBase = info->msrs.kern_gs_base;
818 guest_state->cpl = info->cpl;
820 v3_set_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
822 guest_state->rax = info->vm_regs.rax;
823 guest_state->rip = info->rip;
824 guest_state->rsp = info->vm_regs.rsp;
826 V3_FP_ENTRY_RESTORE(info);
828 #ifdef V3_CONFIG_SYMCALL
829 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
830 update_irq_entry_state(info);
834 update_irq_entry_state(info);
837 #ifdef V3_CONFIG_TM_FUNC
838 v3_tm_check_intr_state(info, guest_ctrl, guest_state);
845 PrintDebug(info->vm_info, info, "SVM Entry to CS=%p rip=%p...\n",
846 (void *)(addr_t)info->segments.cs.base,
847 (void *)(addr_t)info->rip);
850 #ifdef V3_CONFIG_SYMCALL
851 if (info->sym_core_state.symcall_state.sym_call_active == 1) {
852 if (guest_ctrl->guest_ctrl.V_IRQ == 1) {
853 V3_Print(info->vm_info, info, "!!! Injecting Interrupt during Sym call !!!\n");
858 v3_svm_config_tsc_virtualization(info);
860 //V3_Print(info->vm_info, info, "Calling v3_svm_launch\n");
862 uint64_t entry_tsc = 0;
863 uint64_t exit_tsc = 0;
865 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
866 v3_pwrstat_telemetry_enter(info);
869 #ifdef V3_CONFIG_PMU_TELEMETRY
870 v3_pmu_telemetry_enter(info);
876 v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[V3_Get_CPU()]);
880 #ifdef V3_CONFIG_PMU_TELEMETRY
881 v3_pmu_telemetry_exit(info);
884 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
885 v3_pwrstat_telemetry_exit(info);
888 guest_cycles = exit_tsc - entry_tsc;
892 //V3_Print(info->vm_info, info, "SVM Returned: Exit Code: %x, guest_rip=%lx\n", (uint32_t)(guest_ctrl->exit_code), (unsigned long)guest_state->rip);
894 v3_last_exit = (uint32_t)(guest_ctrl->exit_code);
896 v3_advance_time(info, &guest_cycles);
900 V3_FP_EXIT_SAVE(info);
902 // Save Guest state from VMCB
903 info->rip = guest_state->rip;
904 info->vm_regs.rsp = guest_state->rsp;
905 info->vm_regs.rax = guest_state->rax;
907 info->cpl = guest_state->cpl;
909 info->ctrl_regs.cr0 = guest_state->cr0;
910 info->ctrl_regs.cr2 = guest_state->cr2;
911 info->ctrl_regs.cr3 = guest_state->cr3;
912 info->ctrl_regs.cr4 = guest_state->cr4;
913 info->dbg_regs.dr6 = guest_state->dr6;
914 info->dbg_regs.dr7 = guest_state->dr7;
916 // We do not track this anymore
917 // V_TPR is ignored and we do the logic in the APIC
918 //info->ctrl_regs.cr8 = guest_ctrl->guest_ctrl.V_TPR;
920 info->ctrl_regs.rflags = guest_state->rflags;
921 info->ctrl_regs.efer = guest_state->efer;
923 /* Synchronize MSRs */
924 info->msrs.star = guest_state->star;
925 info->msrs.lstar = guest_state->lstar;
926 info->msrs.sfmask = guest_state->sfmask;
927 info->msrs.kern_gs_base = guest_state->KernelGsBase;
929 v3_get_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
930 info->cpu_mode = v3_get_vm_cpu_mode(info);
931 info->mem_mode = v3_get_vm_mem_mode(info);
934 // save exit info here
935 exit_code = guest_ctrl->exit_code;
936 exit_info1 = guest_ctrl->exit_info1;
937 exit_info2 = guest_ctrl->exit_info2;
939 #ifdef V3_CONFIG_SYMCALL
940 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
941 update_irq_exit_state(info);
944 update_irq_exit_state(info);
947 // reenable global interrupts after vm exit
950 // Conditionally yield the CPU if the timeslice has expired
953 // This update timers is for time-dependent handlers
954 // if we're slaved to host time
955 v3_advance_time(info, NULL);
956 v3_update_timers(info);
960 int ret = v3_handle_svm_exit(info, exit_code, exit_info1, exit_info2);
963 PrintError(info->vm_info, info, "Error in SVM exit handler (ret=%d)\n", ret);
964 PrintError(info->vm_info, info, " last Exit was %d (exit code=0x%llx)\n", v3_last_exit, (uint64_t) exit_code);
971 if (info->timeouts.timeout_active) {
972 /* Check to see if any timeouts have expired */
973 v3_handle_timeouts(info, guest_cycles);
976 #ifdef V3_CONFIG_MEM_TRACK
977 v3_mem_track_exit(info);
984 int v3_start_svm_guest(struct guest_info * info) {
988 // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
989 // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
991 PrintDebug(info->vm_info, info, "Starting SVM core %u (on logical core %u)\n", info->vcpu_id, info->pcpu_id);
994 #ifdef V3_CONFIG_MULTIBOOT
995 if (v3_setup_multiboot_core_for_boot(info)) {
996 PrintError(info->vm_info, info, "Failed to setup Multiboot core...\n");
1001 #ifdef V3_CONFIG_HVM
1002 if (v3_setup_hvm_hrt_core_for_boot(info)) {
1003 PrintError(info->vm_info, info, "Failed to setup HRT core...\n");
1010 if (info->core_run_state == CORE_STOPPED) {
1012 if (info->vcpu_id == 0) {
1013 info->core_run_state = CORE_RUNNING;
1015 PrintDebug(info->vm_info, info, "SVM core %u (on %u): Waiting for core initialization\n", info->vcpu_id, info->pcpu_id);
1019 // Compiler must not optimize away this read
1020 while (*((volatile int *)(&info->core_run_state)) == CORE_STOPPED) {
1022 if (info->vm_info->run_state == VM_STOPPED) {
1023 // The VM was stopped before this core was initialized.
1027 V3_STILL_NO_WORK(info);
1029 //PrintDebug(info->vm_info, info, "SVM core %u: still waiting for INIT\n", info->vcpu_id);
1032 V3_HAVE_WORK_AGAIN(info);
1034 PrintDebug(info->vm_info, info, "SVM core %u(on %u) initialized\n", info->vcpu_id, info->pcpu_id);
1036 // We'll be paranoid about race conditions here
1037 v3_wait_at_barrier(info);
1045 PrintDebug(info->vm_info, info, "SVM core %u(on %u): I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
1046 info->vcpu_id, info->pcpu_id,
1047 info->segments.cs.selector, (void *)(info->segments.cs.base),
1048 info->segments.cs.limit, (void *)(info->rip));
1052 PrintDebug(info->vm_info, info, "SVM core %u: Launching SVM VM (vmcb=%p) (on cpu %u)\n",
1053 info->vcpu_id, (void *)info->vmm_data, info->pcpu_id);
1055 #ifdef V3_CONFIG_DEBUG_SVM
1056 PrintDebugVMCB((vmcb_t*)(info->vmm_data));
1059 v3_start_time(info);
1062 if (info->vm_info->run_state == VM_STOPPED) {
1063 info->core_run_state = CORE_STOPPED;
1068 #ifdef V3_CONFIG_HVM
1069 if (v3_handle_hvm_reset(info) > 0) {
1074 #ifdef V3_CONFIG_MULTIBOOT
1075 if (v3_handle_multiboot_reset(info) > 0) {
1080 if (svm_handle_standard_reset(info) > 0 ) {
1086 #ifdef V3_CONFIG_PMU_TELEMETRY
1087 v3_pmu_telemetry_start(info);
1090 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
1091 v3_pwrstat_telemetry_start(info);
1094 if (v3_svm_enter(info) == -1 ) {
1095 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
1097 addr_t linear_addr = 0;
1099 info->vm_info->run_state = VM_ERROR;
1101 V3_Print(info->vm_info, info, "SVM core %u: SVM ERROR!!\n", info->vcpu_id);
1103 v3_print_guest_state(info);
1105 V3_Print(info->vm_info, info, "SVM core %u: SVM Exit Code: %p\n", info->vcpu_id, (void *)(addr_t)guest_ctrl->exit_code);
1107 V3_Print(info->vm_info, info, "SVM core %u: exit_info1 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info1));
1108 V3_Print(info->vm_info, info, "SVM core %u: exit_info1 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
1110 V3_Print(info->vm_info, info, "SVM core %u: exit_info2 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info2));
1111 V3_Print(info->vm_info, info, "SVM core %u: exit_info2 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
1113 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
1115 if (info->mem_mode == PHYSICAL_MEM) {
1116 v3_gpa_to_hva(info, linear_addr, &host_addr);
1117 } else if (info->mem_mode == VIRTUAL_MEM) {
1118 v3_gva_to_hva(info, linear_addr, &host_addr);
1121 V3_Print(info->vm_info, info, "SVM core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
1123 V3_Print(info->vm_info, info, "SVM core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
1124 v3_dump_mem((uint8_t *)host_addr, 15);
1126 v3_print_stack(info);
1131 v3_wait_at_barrier(info);
1134 if (info->vm_info->run_state == VM_STOPPED) {
1135 info->core_run_state = CORE_STOPPED;
1142 if ((info->num_exits % 50000) == 0) {
1143 V3_Print(info->vm_info, info, "SVM Exit number %d\n", (uint32_t)info->num_exits);
1144 v3_print_guest_state(info);
1150 #ifdef V3_CONFIG_PMU_TELEMETRY
1151 v3_pmu_telemetry_end(info);
1154 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
1155 v3_pwrstat_telemetry_end(info);
1157 // Need to take down the other cores on error...
1165 int v3_reset_svm_vm_core(struct guest_info * core, addr_t rip) {
1168 // Write the RIP, CS, and descriptor
1169 // assume the rest is already good to go
1171 // vector VV -> rip at 0
1173 // This means we start executing at linear address VV000
1175 // So the selector needs to be VV00
1176 // and the base needs to be VV000
1179 core->segments.cs.selector = rip << 8;
1180 core->segments.cs.limit = 0xffff;
1181 core->segments.cs.base = rip << 12;
1191 /* Checks machine SVM capability */
1192 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
1193 int v3_is_svm_capable() {
1194 uint_t vm_cr_low = 0, vm_cr_high = 0;
1195 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1197 v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1199 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_EXT_FEATURE_IDS_ecx=0x%x\n", ecx);
1201 if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
1202 V3_Print(VM_NONE, VCORE_NONE, "SVM Not Available\n");
1205 v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
1207 PrintDebug(VM_NONE, VCORE_NONE, "SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
1209 if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
1210 V3_Print(VM_NONE, VCORE_NONE, "SVM is available but is disabled.\n");
1212 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1214 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
1216 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
1217 V3_Print(VM_NONE, VCORE_NONE, "SVM BIOS Disabled, not unlockable\n");
1219 V3_Print(VM_NONE, VCORE_NONE, "SVM is locked with a key\n");
1224 V3_Print(VM_NONE, VCORE_NONE, "SVM is available and enabled.\n");
1226 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1227 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_eax=0x%x\n", eax);
1228 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_ebx=0x%x\n", ebx);
1229 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_ecx=0x%x\n", ecx);
1230 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
1237 static int has_svm_nested_paging() {
1238 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1240 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1242 //PrintDebug(VM_NONE, VCORE_NONE, "CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
1244 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
1245 V3_Print(VM_NONE, VCORE_NONE, "SVM Nested Paging not supported\n");
1248 V3_Print(VM_NONE, VCORE_NONE, "SVM Nested Paging supported\n");
1255 void v3_init_svm_cpu(int cpu_id) {
1257 extern v3_cpu_arch_t v3_cpu_types[];
1259 // Enable SVM on the CPU
1260 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
1261 msr.e_reg.low |= EFER_MSR_svm_enable;
1262 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
1264 V3_Print(VM_NONE, VCORE_NONE, "SVM Enabled\n");
1266 // Setup the host state save area
1267 host_vmcbs[cpu_id] = (addr_t)V3_AllocPages(4); // need not be shadow-safe, not exposed to guest
1269 if (!host_vmcbs[cpu_id]) {
1270 PrintError(VM_NONE, VCORE_NONE, "Failed to allocate VMCB\n");
1275 // msr.e_reg.high = 0;
1276 //msr.e_reg.low = (uint_t)host_vmcb;
1277 msr.r_reg = host_vmcbs[cpu_id];
1279 PrintDebug(VM_NONE, VCORE_NONE, "Host State being saved at %p\n", (void *)host_vmcbs[cpu_id]);
1280 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
1283 if (has_svm_nested_paging() == 1) {
1284 v3_cpu_types[cpu_id] = V3_SVM_REV3_CPU;
1286 v3_cpu_types[cpu_id] = V3_SVM_CPU;
1292 void v3_deinit_svm_cpu(int cpu_id) {
1294 extern v3_cpu_arch_t v3_cpu_types[];
1296 // reset SVM_VM_HSAVE_PA_MSR
1297 // Does setting it to NULL disable??
1299 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
1302 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
1303 msr.e_reg.low &= ~EFER_MSR_svm_enable;
1304 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
1306 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
1308 V3_FreePages((void *)host_vmcbs[cpu_id], 4);
1310 V3_Print(VM_NONE, VCORE_NONE, "Host CPU %d host area freed, and SVM disabled\n", cpu_id);
1365 * Test VMSAVE/VMLOAD Latency
1367 #define vmsave ".byte 0x0F,0x01,0xDB ; "
1368 #define vmload ".byte 0x0F,0x01,0xDA ; "
1370 uint32_t start_lo, start_hi;
1371 uint32_t end_lo, end_hi;
1372 uint64_t start, end;
1374 __asm__ __volatile__ (
1376 "movl %%eax, %%esi ; "
1377 "movl %%edx, %%edi ; "
1378 "movq %%rcx, %%rax ; "
1381 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1382 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1393 PrintDebug(core->vm_info, core, "VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
1395 __asm__ __volatile__ (
1397 "movl %%eax, %%esi ; "
1398 "movl %%edx, %%edi ; "
1399 "movq %%rcx, %%rax ; "
1402 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1403 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1415 PrintDebug(core->vm_info, core, "VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
1417 /* End Latency Test */