2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2011, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2011, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Lei Xia <lxia@northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <devices/ethernet.h>
21 #include <devices/pci.h>
22 #include <palacios/vmm.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm_io.h>
25 #include <palacios/vmm_debug.h>
26 #include <palacios/vm_guest_mem.h>
29 #ifndef CONFIG_DEBUG_RTL8139
31 #define PrintDebug(fmts, args...)
36 #define NIC_BASE_ADDR 0xc100
39 #define RTL8139_IDR0 (0x00) /* ID Registers */
40 #define RTL8139_IDR1 (0x01)
41 #define RTL8139_IDR2 (0x02)
42 #define RTL8139_IDR3 (0x03)
43 #define RTL8139_IDR4 (0x04)
44 #define RTL8139_IDR5 (0x05)
46 #define RTL8139_MAR0 (0x08) /* Mulicast Registers*/
47 #define RTL8139_MAR1 (0x09)
48 #define RTL8139_MAR2 (0x0a)
49 #define RTL8139_MAR3 (0x0b)
50 #define RTL8139_MAR4 (0x0c)
51 #define RTL8139_MAR5 (0x0d)
52 #define RTL8139_MAR6 (0x0e)
53 #define RTL8139_MAR7 (0x0f)
55 #define RTL8139_TSD0 (0x10) /* Tx Status of Descriptors */
56 #define RTL8139_TSD1 (0x14)
57 #define RTL8139_TSD2 (0x18)
58 #define RTL8139_TSD3 (0x1c)
60 #define RTL8139_TSAD0 (0x20) /* Tx Start Address of Descriptors */
61 #define RTL8139_TSAD1 (0x24)
62 #define RTL8139_TSAD2 (0x28)
63 #define RTL8139_TSAD3 (0x2c)
65 #define RTL8139_RBSTART (0x30) /* Rx Buffer Start Address */
66 #define RTL8139_ERBCR (0x34) /* Early Rx Byte Count Register */
67 #define RTL8139_ERSR (0x36) /* Early Rx Status Register */
68 #define RTL8139_CR (0x37) /* Command Register */
69 #define RTL8139_CAPR (0x38) /* Current Address of Pkt Read */
70 #define RTL8139_CBR (0x3a) /* Current Buffer Address */
71 #define RTL8139_IMR (0x3c) /* Intrpt Mask Reg */
72 #define RTL8139_ISR (0x3e) /* Intrpt Status Reg */
73 #define RTL8139_TCR (0x40) /* Tx Config Reg */
74 #define RTL8139_RCR (0x44) /* Rx Config Reg */
75 #define RTL8139_TCTR (0x48) /* Timer Count Reg */
76 #define RTL8139_MPC (0x4c) /* Missed Pkt Counter */
77 #define RTL8139_9346CR (0x50) /* 9346 Command Reg */
78 #define RTL8139_CONFIG0 (0x51) /* Config Reg */
79 #define RTL8139_CONFIG1 (0x52)
80 #define RTL8139_TimerInt (0x54) /* Timer Intrpt Reg */
81 #define RTL8139_MSR (0x58) /* Media Status Reg */
82 #define RTL8139_CONFIG3 (0x59)
83 #define RTL8139_CONFIG4 (0x5a)
84 #define RTL8139_MULINT (0x5c) /* Multiple Intrpt Select */
85 #define RTL8139_RERID (0x5e)
86 #define RTL8139_TSAD (0x60) /* Tx Status of All Descriptors */
87 #define RTL8139_BMCR (0x62) /* Basic Mode Control Register */
88 #define RTL8139_BMSR (0x64) /* Basic Mode Status Register */
89 #define RTL8139_ANAR (0x66) /* Auto-Negotiation Advertisement Register */
90 #define RTL8139_ANLPAR (0x68) /* Auto-Negotiation Link Partner Register */
91 #define RTL8139_ANER (0x6a) /* Auto-Negotiation Expansion Register */
92 #define RTL8139_DIS (0x6c) /* Disconnect Counter */
93 #define RTL8139_FCSC (0x6e) /* False Carrier Sense Counter */
94 #define RTL8139_NWAYTR (0x70) /* N-way Test Register */
95 #define RTL8139_REC (0x72) /* RX ER Counter */
96 #define RTL8139_CSCR (0x74) /* CS Config Register */
97 #define RTL8139_PHY1_PARM (0x78) /* PHY parameter */
98 #define RTL8139_TW_PARM (0x7c) /* Twister parameter */
99 #define RTL8139_PHY2_PARM (0x80)
101 #define RTL8139_CRC0 (0x84) /* Power Management CRC Reg for wakeup frame */
102 #define RTL8139_CRC1 (0x85)
103 #define RTL8139_CRC2 (0x86)
104 #define RTL8139_CRC3 (0x87)
105 #define RTL8139_CRC4 (0x88)
106 #define RTL8139_CRC5 (0x89)
107 #define RTL8139_CRC6 (0x8a)
108 #define RTL8139_CRC7 (0x8b)
110 #define RTL8139_Wakeup0 (0x8c) /* Power Management wakeup frame */
111 #define RTL8139_Wakeup1 (0x94)
112 #define RTL8139_Wakeup2 (0x9c)
113 #define RTL8139_Wakeup3 (0xa4)
114 #define RTL8139_Wakeup4 (0xac)
115 #define RTL8139_Wakeup5 (0xb4)
116 #define RTL8139_Wakeup6 (0xbc)
117 #define RTL8139_Wakeup7 (0xc4)
119 #define RTL8139_LSBCRO0 (0xcc) /* LSB of the mask byte of wakeup frame */
120 #define RTL8139_LSBCRO1 (0xcd)
121 #define RTL8139_LSBCRO2 (0xce)
122 #define RTL8139_LSBCRO3 (0xcf)
123 #define RTL8139_LSBCRO4 (0xd0)
124 #define RTL8139_LSBCRO5 (0xd1)
125 #define RTL8139_LSBCRO6 (0xd2)
126 #define RTL8139_LSBCRO7 (0xd3)
128 #define RTL8139_Config5 (0xd8)
131 #define PKT_RX 0x0001
132 #define RX_ERR 0x0002
134 #define TX_ERR 0x0008
135 #define RX_BUFF_OF 0x0010
136 #define RX_UNDERRUN 0x0020
137 #define RX_FIFO_OF 0x0040
138 #define CABLE_LEN_CHNG 0x2000
139 #define TIME_OUT 0x4000
142 #define DESC_SIZE 2048
143 #define TX_FIFO_SIZE (DESC_SIZE * 4)
144 #define RX_FIFO_SIZE (DESC_SIZE * 4)
146 typedef enum {NIC_READY, NIC_REG_POSTED} nic_state_t;
153 TSD_Cdh = 0x10000000,
154 TSD_Owc = 0x20000000,
155 TSD_Tabt = 0x40000000,
156 TSD_Crs = 0x80000000,
160 Rx_Multicast = 0x8000,
161 Rx_Physical = 0x4000,
162 Rx_Broadcast = 0x2000,
163 Rx_BadSymbol = 0x0020,
167 Rx_BadAlign = 0x0002,
168 Rx_StatusOK = 0x0001,
172 /* Transmit Status of All Descriptors (TSAD) Register */
174 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
175 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
176 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
177 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
178 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
179 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
180 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
181 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
182 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
183 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
184 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
185 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
186 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
187 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
188 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
189 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
202 ISR_Timeout = 0x4000,
216 CMD9346_Unlock = 0xC0,
222 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
224 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
225 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
226 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
227 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
229 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
230 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
231 TxClearAbt = (1 << 0), /* Clear abort (WO) */
232 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
233 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
235 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
239 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
240 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
241 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
242 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
243 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
244 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
245 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
246 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
247 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
250 /* Bits in RxConfig. */
254 AcceptBroadcast = 0x08,
255 AcceptMulticast = 0x04,
257 AcceptAllPhys = 0x01,
260 #define RTL8139_PCI_REVID_8139 0x10
262 #define SET_MASKED(input, mask, curr) \
263 (((input) & ~(mask)) | ((curr) & (mask)))
265 /* arg % size for size which is a power of 2 */
266 #define MOD2(input, size) \
267 ((input) & (size - 1))
270 /* Size is 64 * 16bit words */
271 #define EEPROM_9346_ADDR_BITS 6
272 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
273 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
275 enum Chip9346Operation
277 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
278 Chip9346_op_read = 0x80, /* 10 AAAAAA */
279 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
280 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
281 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
282 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
283 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
289 Chip9346_enter_command_mode,
290 Chip9346_read_command,
291 Chip9346_data_read, /* from output register */
292 Chip9346_data_write, /* to input register, then to contents at specified address */
293 Chip9346_data_write_all, /* to input register, then filling contents */
298 uint16_t contents[EEPROM_9346_SIZE];
311 struct rtl8139_regs {
358 }__attribute__((packed));
359 }__attribute__((packed));
366 nic_state_t dev_state;
368 struct v3_vm_info * vm;
369 struct pci_device * pci_dev;
370 struct vm_device * pci_bus;
371 struct vm_device * dev;
373 struct nic_statistics statistic;
375 struct rtl8139_regs regs;
376 struct EEprom9346 eeprom;
378 uint8_t tx_fifo[TX_FIFO_SIZE];
379 uint8_t rx_fifo[RX_FIFO_SIZE];
382 uint8_t mac[ETH_ALEN];
384 struct v3_dev_net_ops *net_ops;
389 static void rtl8139_reset(struct vm_device *dev);
391 static void dump_state(struct vm_device *dev)
393 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
394 PrintDebug("====RTL8139: Dumping State Begin==========\n");
395 PrintDebug("Registers\n");
398 reg = (uchar_t *)&nic_state->regs;
400 for(i = 0; i < sizeof(struct nic_regs); i++)
402 PrintDebug("Register[%d] = 0x%2x\n", i, (int)reg[i]);
405 PrintDebug("====RTL8139: Dumping State End==========\n");
408 static void rtl8139_update_irq(struct rtl8139_state *nic_state)
410 struct pci_device *pdev = nic_state->pci_dev;
413 irq_line = pdev->configs[PCI_INTERRUPT_LINE];
414 int isr = ((nic_state->regs.isr & nic_state->regs.imr) & 0xffff);
419 v3_raise_irq(dev->vm, irq_line);
420 PrintDebug("VNIC: RaiseIrq %d: isr: 0x%04x imr : 0x%04x\n", irq_line, nic_state->regs.isr, nic_state->regs.imr);
422 PrintError("RTL8139: IRQ_Line: %d\n", irq_line);
429 static void prom9346_decode_command(struct EEprom9346 *eeprom, uint8_t command)
431 PrintDebug("RTL8139: eeprom command 0x%02x\n", command);
433 switch (command & Chip9346_op_mask)
435 case Chip9346_op_read:
437 eeprom->address = command & EEPROM_9346_ADDR_MASK;
438 eeprom->output = eeprom->contents[eeprom->address];
441 eeprom->mode = Chip9346_data_read;
442 PrintDebug("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
443 eeprom->address, eeprom->output);
447 case Chip9346_op_write:
449 eeprom->address = command & EEPROM_9346_ADDR_MASK;
452 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
453 PrintDebug("RTL8139: eeprom begin write to address 0x%02x\n",
458 eeprom->mode = Chip9346_none;
459 switch (command & Chip9346_op_ext_mask)
461 case Chip9346_op_write_enable:
462 PrintDebug("RTL8139: eeprom write enabled\n");
464 case Chip9346_op_write_all:
465 PrintDebug("RTL8139: eeprom begin write all\n");
467 case Chip9346_op_write_disable:
468 PrintDebug("RTL8139: eeprom write disabled\n");
475 static void prom9346_shift_clock(struct EEprom9346 *eeprom)
477 int bit = eeprom->eedi?1:0;
481 PrintDebug("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo);
483 switch (eeprom->mode)
485 case Chip9346_enter_command_mode:
488 eeprom->mode = Chip9346_read_command;
491 PrintDebug("eeprom: +++ synchronized, begin command read\n");
495 case Chip9346_read_command:
496 eeprom->input = (eeprom->input << 1) | (bit & 1);
497 if (eeprom->tick == 8)
499 prom9346_decode_command(eeprom, eeprom->input & 0xff);
503 case Chip9346_data_read:
504 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
505 eeprom->output <<= 1;
506 if (eeprom->tick == 16)
509 // the FreeBSD drivers (rl and re) don't explicitly toggle
510 // CS between reads (or does setting Cfg9346 to 0 count too?),
511 // so we need to enter wait-for-command state here
512 eeprom->mode = Chip9346_enter_command_mode;
516 PrintDebug("eeprom: +++ end of read, awaiting next command\n");
518 // original behaviour
520 eeprom->address &= EEPROM_9346_ADDR_MASK;
521 eeprom->output = eeprom->contents[eeprom->address];
524 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
525 eeprom->address, eeprom->output));
530 case Chip9346_data_write:
531 eeprom->input = (eeprom->input << 1) | (bit & 1);
532 if (eeprom->tick == 16)
534 PrintDebug("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
535 eeprom->address, eeprom->input);
537 eeprom->contents[eeprom->address] = eeprom->input;
538 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
544 case Chip9346_data_write_all:
545 eeprom->input = (eeprom->input << 1) | (bit & 1);
546 if (eeprom->tick == 16)
549 for (i = 0; i < EEPROM_9346_SIZE; i++)
551 eeprom->contents[i] = eeprom->input;
553 PrintDebug("RTL8139: eeprom filled with data=0x%04x\n",
556 eeprom->mode = Chip9346_enter_command_mode;
567 static int prom9346_get_wire(struct vm_device *dev)
569 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
570 struct EEprom9346 *eeprom = &(nic_state->eeprom);
578 static void prom9346_set_wire(struct vm_device *dev, int eecs, int eesk, int eedi)
580 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
581 struct EEprom9346 *eeprom = &(nic_state->eeprom);
582 uint8_t old_eecs = eeprom->eecs;
583 uint8_t old_eesk = eeprom->eesk;
589 PrintDebug("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
590 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo);
592 if (!old_eecs && eecs)
594 /* Synchronize start */
598 eeprom->mode = Chip9346_enter_command_mode;
600 PrintDebug("=== eeprom: begin access, enter command mode\n");
605 PrintDebug("=== eeprom: end access\n");
609 if (!old_eesk && eesk)
612 prom9346_shift_clock(eeprom);
616 static void rtl8139_9346cr_write(struct vm_device *dev, uint32_t val)
618 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
622 PrintDebug("RTL8139: 9346CR write val=0x%02x\n", val);
624 /* mask unwriteable bits */
625 val = SET_MASKED(val, 0x31, nic_state->regs.cmd9346);
627 uint32_t opmode = val & 0xc0;
628 uint32_t eeprom_val = val & 0xf;
630 if (opmode == 0x80) {
632 int eecs = (eeprom_val & 0x08)?1:0;
633 int eesk = (eeprom_val & 0x04)?1:0;
634 int eedi = (eeprom_val & 0x02)?1:0;
635 prom9346_set_wire(dev, eecs, eesk, eedi);
636 } else if (opmode == 0x40) {
642 nic_state->regs.cmd9346 = val;
645 static uint32_t rtl8139_9346cr_read(struct vm_device *dev)
647 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
648 uint32_t ret = nic_state->regs.cmd9346;
649 uint32_t opmode = ret & 0xc0;
654 int eedo = prom9346_get_wire(dev);
665 PrintDebug("RTL8139: 9346CR read val=0x%02x\n", ret);
672 static int rtl8139_receiver_enabled(struct vm_device *dev)
674 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
676 return nic_state->regs.cmd & CMD_Re;
679 static int rtl8139_rxwrap(struct vm_device *dev)
681 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
683 // wrapping enabled; assume 1.5k more buffer space if size < 64K
684 return (nic_state->regs.rcr & (1 << 7));
687 static void rtl8139_rxbuf_write(struct vm_device *dev, const void *buf, int size)
689 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
690 struct nic_regs *regs = &(nic_state->regs);
692 addr_t guestpa, host_rxbuf;
694 guestpa = (addr_t)regs->rbstart;
695 guest_pa_to_host_va(dev->vm, guestpa, &host_rxbuf);
697 //wrap to the front of rx buffer
698 if (regs->cbr + size > nic_state->rx_bufsize)
700 wrap = MOD2(regs->cbr + size, nic_state->rx_bufsize);
702 if (wrap && !(nic_state->rx_bufsize < 64*1024 && rtl8139_rxwrap(dev)))
704 PrintDebug("RTL8139: rx packet wrapped in buffer at %d\n", size-wrap);
708 memcpy((void *)(host_rxbuf + regs->cbr), buf, size-wrap);
711 // reset buffer pointer
714 memcpy((void *)(host_rxbuf + regs->cbr), buf + (size-wrap), wrap);
722 memcpy((void *)(host_rxbuf + regs->cbr), buf, size);
727 #define POLYNOMIAL 0x04c11db6
730 static int compute_mcast_idx(const uint8_t *ep)
737 for (i = 0; i < 6; i++) {
739 for (j = 0; j < 8; j++) {
740 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
744 crc = ((crc ^ POLYNOMIAL) | carry);
749 static void vnic_receive(struct vm_device *dev, const uchar_t *pkt, uint_t length)
751 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
752 struct nic_regs *regs = &(nic_state->regs);
753 uint_t rxbufsize = nic_state->rx_bufsize;
754 uint32_t header, val;
755 uint8_t bcast_addr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
757 if (regs->rcr & AcceptAllPhys) {
758 PrintDebug("RTL8139: packet received in promiscuous mode\n");
760 if (!memcmp(pkt, bcast_addr, 6)) {
761 if (!(regs->rcr & AcceptBroadcast))
763 PrintDebug("RTL8139: broadcast packet rejected\n");
766 header |= Rx_Broadcast;
767 PrintDebug("RTL8139: broadcast packet received\n");
768 } else if (pkt[0] & 0x01) {
770 if (!(regs->rcr & AcceptMulticast))
772 PrintDebug("RTL8139: multicast packet rejected\n");
776 int mcast_idx = compute_mcast_idx(pkt);
778 if (!(regs->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
780 PrintDebug("RTL8139: multicast address mismatch\n");
783 header |= Rx_Multicast;
784 PrintDebug("RTL8139: multicast packet received\n");
785 } else if (regs->id[0] == pkt[0] &&
786 regs->id[1] == pkt[1] &&
787 regs->id[2] == pkt[2] &&
788 regs->id[3] == pkt[3] &&
789 regs->id[4] == pkt[4] &&
790 regs->id[5] == pkt[5]) {
791 if (!(regs->rcr & AcceptMyPhys))
793 PrintDebug("RTL8139: rejecting physical address matching packet\n");
797 header |= Rx_Physical;
798 PrintDebug("RTL8139: physical address matching packet received\n");
800 PrintDebug("RTL8139: unknown packet\n");
806 PrintDebug("RTL8139: in ring Rx mode\n");
808 int avail = MOD2(rxbufsize + regs->capr - regs->cbr, rxbufsize);
810 if (avail != 0 && length + 8 >= avail)
812 PrintError("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
813 rxbufsize, regs->cbr, regs->capr, avail, length + 8);
815 regs->isr |= ISR_Rxovw;
817 rtl8139_update_irq(dev);
821 header |= Rx_StatusOK;
822 header |= ((length << 16) & 0xffff0000);
824 rtl8139_rxbuf_write(dev, (uint8_t *)&header, 4);
826 rtl8139_rxbuf_write(dev, pkt, length);
828 val = V3_Crc32(0, (char *)pkt, length);
830 rtl8139_rxbuf_write(dev, (uint8_t *)&val, 4);
832 // correct buffer write pointer
833 regs->cbr = MOD2((regs->cbr + 3) & ~0x3, rxbufsize);
835 PrintDebug("RTL8139: received: rx buffer length %d CBR: 0x%04x CAPR: 0x%04x\n",
836 rxbufsize, regs->cbr, regs->capr);
839 regs->isr |= ISR_Rok;
841 nic_state->pkts_rcvd++;
843 rtl8139_update_irq(dev);
846 static int netif_input(uchar_t *pkt, uint_t size)
848 PrintDebug("RTL8139: packet received!\n");
850 if (!rtl8139_receiver_enabled(current_vnic)){
851 PrintDebug("RTL8139: receiver disabled\n");
854 vnic_receive(current_vnic, pkt, size);
859 static void rtl8139_reset_rxbuf(struct vm_device *dev, uint32_t bufsize)
861 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
862 struct nic_regs *regs = &(nic_state->regs);
864 nic_state->rx_bufsize = bufsize;
869 static void rtl8139_rcr_write(struct vm_device *dev, uint32_t val)
871 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
873 PrintDebug("RTL8139: RCR write val=0x%08x\n", val);
875 val = SET_MASKED(val, 0xf0fc0040, nic_state->regs.rcr);
877 nic_state->regs.rcr = val;
880 uchar_t rblen = (regs->rcr >> 11) & 0x3;
884 rxbufsize = 1024 * 8 + 16;
887 rxbufsize = 1024 * 16 + 16;
890 rxbufsize = 1024 * 32 + 16;
893 rxbufsize = 1024 * 64 + 16;
898 // reset buffer size and read/write pointers
899 rtl8139_reset_rxbuf(dev, 8192 << ((nic_state->regs.rcr >> 11) & 0x3));
901 PrintDebug("RTL8139: RCR write reset buffer size to %d\n", nic_state->rx_bufsize);
904 static void rtl8139_reset(struct rtl8139_state *nic_state)
906 struct rtl8139_regs *regs = &(nic_state->regs);
909 PrintDebug("Rtl8139: Reset\n");
911 /* restore MAC address */
912 memcpy(regs->id, nic_state->mac, ETH_ALEN);
913 memset(regs->mult, 0xff, 8);
918 rtl8139_update_irq(nic_state);
921 nic_state->eeprom.contents[0] = 0x8129;
923 // PCI vendor and device ID
924 nic_state->eeprom.contents[1] = 0x10ec;
925 nic_state->eeprom.contents[2] = 0x8139;
927 nic_state->eeprom.contents[7] = nic_state->mac[0] | nic_state->mac[1] << 8;
928 nic_state->eeprom.contents[8] = nic_state->mac[2] | nic_state->mac[3] << 8;
929 nic_state->eeprom.contents[9] = nic_state->mac[4] | nic_state->mac[5] << 8;
931 for (i = 0; i < 4; ++i)
933 regs->tsd[i] = TSD_Own;
938 rtl8139_reset_rxbuf(nic_state, 1024*8);
943 regs->tcr |= ((0x1d << 26) | (0x1 << 22)); // RTL-8139D
944 regs->rerid = RTL8139_PCI_REVID_8139;
946 regs->cmd = CMD_Rst; //RxBufEmpty bit is calculated on read from ChipCmd
948 regs->config[0] = 0x0 | (1 << 4); // No boot ROM
949 regs->config[1] = 0xC; //IO mapped and MEM mapped registers available
950 //regs->config[1] = 0x4; //Only IO mapped registers available
951 regs->config3[0] = 0x1; // fast back-to-back compatible
952 regs->config3[1] = 0x0;
955 regs->cscr = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
957 //0x3100 : 100Mbps, full duplex, autonegotiation. 0x2100 : 100Mbps, full duplex
958 regs->bmcr = 0x1000; // autonegotiation
961 regs->bmsr |= 0x0020; // autonegotiation completed
962 regs->bmsr |= 0x0004; // link is up
964 regs->anar = 0x05e1; // all modes, full duplex
965 regs->anlpar = 0x05e1; // all modes, full duplex
966 regs->aner = 0x0001; // autonegotiation supported
968 // reset timer and disable timer interrupt
972 nic_state->pkts_rcvd = 0;
975 static void init_rtl8139_regs(struct rtl8139_state *nic_state)
977 nic_state->regs.imr = 0x00;
978 nic_state->regs.tsd[0] = nic_state->regs.tsd[1] = nic_state->regs.tsd[2] = nic_state->regs.tsd[3] = TSD_Own;
979 nic_state->pkts_rcvd = 0;
982 for(i = 0; i < 6; i++)
983 nic_state->regs.id[i] = nic_state->mac_addr[i] = mac[i];
984 for(i = 0; i < 8; i++)
985 nic_state->regs.mult[i] = 0xff;
987 nic_state->regs.rerid = RTL8139_PCI_REVID_8139;
988 nic_state->regs.tcr |= ((0x1d << 26) | (0x1 << 22));
996 static int rtl8139_config_writeable(struct vm_device *dev)
998 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1000 if (nic_state->regs.cmd9346 & CMD9346_Unlock)
1005 PrintDebug("RTL8139: Configuration registers are unwriteable\n");
1012 static int rtl8139_transmitter_enabled(struct vm_device *dev)
1014 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1016 return nic_state->regs.cmd & CMD_Te;
1019 static bool rtl8139_rxbufempty(struct vm_device *dev)
1021 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1022 struct nic_regs *regs = &(nic_state->regs);
1025 unread = MOD2(regs->cbr + nic_state->rx_bufsize - regs->capr, nic_state->rx_bufsize);
1029 PrintDebug("RTL8139: receiver buffer data available 0x%04x\n", unread);
1033 PrintDebug("RTL8139: receiver buffer is empty\n");
1038 static uint32_t rtl8139_cmd_read(struct vm_device *dev)
1040 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1041 uint32_t ret = nic_state->regs.cmd;
1043 if (rtl8139_rxbufempty(dev))
1046 PrintDebug("RTL8139: Cmd read val=0x%04x\n", ret);
1051 static void rtl8139_cmd_write(struct vm_device *dev, uint32_t val)
1053 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1057 PrintDebug("RTL8139: Cmd write val=0x%08x\n", val);
1061 PrintDebug("RTL8139: Cmd reset\n");
1066 PrintDebug("RTL8139: Cmd enable receiver\n");
1068 //s->currCPlusRxDesc = 0;
1072 PrintDebug("RTL8139: Cmd enable transmitter\n");
1074 //s->currCPlusTxDesc = 0;
1077 val = SET_MASKED(val, 0xe3, nic_state->regs.cmd);
1080 nic_state->regs.cmd = val;
1083 static int rtl8139_send_packet(struct vm_device *dev, int descriptor)
1085 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1086 struct nic_regs *regs = &(nic_state->regs);
1089 addr_t pkt_gpa = 0, hostva = 0;
1092 if (!rtl8139_transmitter_enabled(dev))
1094 PrintError("RTL8139: fail to send from descriptor %d: transmitter disabled\n", descriptor);
1098 if (regs->tsd[descriptor] & TSD_Own)
1100 PrintError("RTL8139: fail to send from descriptor %d: owned by host\n", descriptor);
1104 txsize = regs->tsd[descriptor] & 0x1fff;
1105 pkt_gpa = (addr_t) regs->tsad[descriptor];
1107 PrintDebug("RTL8139: sending %d bytes from guest memory at 0x%08x\n", txsize, regs->tsad[descriptor]);
1109 guest_pa_to_host_va(dev->vm, (addr_t)pkt_gpa, &hostva);
1110 pkt = (uchar_t *)hostva;
1112 for(i = 0; i < txsize; i++)
1114 PrintDebug("%x ", pkt[i]);
1118 if (TxLoopBack == (regs->tcr & TxLoopBack)){ //loopback test
1119 PrintDebug(("RTL8139: transmit loopback mode\n"));
1120 vnic_receive(dev, pkt, txsize);
1122 if (V3_SEND_PKT(pkt, txsize) == 0){
1123 PrintDebug("RTL8139: Sent %d bytes from descriptor %d\n", txsize, descriptor);
1125 PrintError("Rtl8139: Sending packet error: 0x%p\n", pkt);
1129 regs->tsd[descriptor] |= TSD_Tok;
1130 regs->tsd[descriptor] |= TSD_Own;
1132 nic_state->regs.isr |= ISR_Tok;
1133 rtl8139_update_irq(dev);
1138 //write to transmit status registers
1139 static void rtl8139_tsd_write(struct vm_device *dev, uint8_t descriptor, uint32_t val)
1141 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1144 if (rtl8139_transmitter_enabled(dev))
1146 PrintDebug("RTL8139: TxStatus write val=0x%08x descriptor=%d\n", val, descriptor);
1148 nic_state->regs.tsd[descriptor] = val;
1154 PrintDebug("RTL8139: TSD write val=0x%08x descriptor=%d\n", val, descriptor);
1156 // mask read-only bits
1158 val = SET_MASKED(val, 0x00c00000, nic_state->regs.tsd[descriptor]);
1160 nic_state->regs.tsd[descriptor] = val;
1162 rtl8139_send_packet(dev, descriptor);
1165 //transmit status of all descriptors
1166 static uint16_t rtl8139_tsad_read(struct vm_device *dev)
1169 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1170 struct nic_regs *regs = &(nic_state->regs);
1172 ret = ((regs->tsd[3] & TSD_Tok)?TSD_Tok:0)
1173 |((regs->tsd[2] & TSD_Tok)?TSAD_TOK2:0)
1174 |((regs->tsd[1] & TSD_Tok)?TSAD_TOK1:0)
1175 |((regs->tsd[0] & TSD_Tok)?TSAD_TOK0:0)
1177 |((regs->tsd[3] & TSD_Tun)?TSAD_TUN3:0)
1178 |((regs->tsd[2] & TSD_Tun)?TSAD_TUN2:0)
1179 |((regs->tsd[1] & TSD_Tun)?TSAD_TUN1:0)
1180 |((regs->tsd[0] & TSD_Tun)?TSAD_TUN0:0)
1182 |((regs->tsd[3] & TSD_Tabt)?TSAD_TABT3:0)
1183 |((regs->tsd[2] & TSD_Tabt)?TSAD_TABT2:0)
1184 |((regs->tsd[1] & TSD_Tabt)?TSAD_TABT1:0)
1185 |((regs->tsd[0] & TSD_Tabt)?TSAD_TABT0:0)
1187 |((regs->tsd[3] & TSD_Own)?TSAD_OWN3:0)
1188 |((regs->tsd[2] & TSD_Own)?TSAD_OWN2:0)
1189 |((regs->tsd[1] & TSD_Own)?TSAD_OWN1:0)
1190 |((regs->tsd[0] & TSD_Own)?TSAD_OWN0:0) ;
1193 PrintDebug("RTL8139: tsad read val=0x%04x\n", (int)ret);
1198 //interrupt mask register
1199 static void rtl8139_imr_write(struct vm_device *dev, uint32_t val)
1201 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1203 PrintDebug("RTL8139: IMR write val=0x%04x\n", val);
1205 /* mask unwriteable bits */
1206 val = SET_MASKED(val, 0x1e00, nic_state->regs.imr);
1208 nic_state->regs.imr = val;
1210 rtl8139_update_irq(dev);
1213 static void rtl8139_isr_write(struct vm_device *dev, uint32_t val)
1215 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1216 struct nic_regs *regs = &(nic_state->regs);
1218 PrintDebug("RTL8139: ISR write val=0x%04x\n", val);
1222 // writing to ISR has no effect
1227 uint16_t newisr = regs->isr & ~val;
1229 /* mask unwriteable bits */
1230 newisr = SET_MASKED(newisr, 0x1e00, regs->isr);
1232 /* writing 1 to interrupt status register bit clears it */
1234 rtl8139_update_irq(dev);
1237 rtl8139_update_irq(dev);
1241 static uint32_t rtl8139_isr_read(struct vm_device *dev)
1243 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1244 uint32_t ret = (uint32_t)nic_state->regs.isr;
1246 PrintDebug("RTL8139: ISR read val=0x%04x\n", ret);
1249 // reading ISR clears all interrupts
1250 nic_state->regs.isr = 0;
1252 rtl8139_update_irq(dev);
1259 static void rtl8139_capr_write(struct vm_device *dev, uint32_t val)
1261 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1263 PrintDebug("RTL8139: CAPR write val=0x%04x\n", val);
1265 // this value is off by 16
1266 nic_state->regs.capr = MOD2(val + 0x10, nic_state->rx_bufsize);
1268 PrintDebug("RTL 8139: CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
1269 nic_state->rx_bufsize, nic_state->regs.cbr, nic_state->regs.capr);
1272 static uint32_t rtl8139_capr_read(struct vm_device *dev)
1274 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1276 /* this value is off by 16 */
1277 uint32_t ret = nic_state->regs.capr - 0x10;
1279 PrintDebug("RTL8139: CAPR read val=0x%04x\n", ret);
1284 typedef enum {read, write} opr_t;
1285 static bool need_hook(int port, opr_t op)
1308 case RTL8139_Config5:
1318 static int rtl8139_mmio_write(addr_t guest_addr, void * src, uint_t length, void * priv_data)
1322 struct vm_device *dev = (struct vm_device *)priv_data;
1323 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1325 port = guest_addr & 0xff;
1327 memcpy(&val, src, length);
1329 PrintDebug("rtl8139 mmio write: addr:0x%x (%u bytes): 0x%x\n", (int)guest_addr, length, val);
1333 nic_state->regs.id[0] = val & 0xff;
1336 nic_state->regs.id[1] = val & 0xff;
1339 nic_state->regs.id[2] = val & 0xff;
1342 nic_state->regs.id[3] = val & 0xff;
1345 nic_state->regs.id[4] = val & 0xff;
1348 nic_state->regs.id[5] = val & 0xff;
1351 nic_state->regs.mult[0] = val & 0xff;
1354 nic_state->regs.mult[1] = val & 0xff;
1357 nic_state->regs.mult[2] = val & 0xff;
1360 nic_state->regs.mult[3] = val & 0xff;
1363 nic_state->regs.mult[4] = val & 0xff;
1366 nic_state->regs.mult[5] = val & 0xff;
1369 nic_state->regs.mult[6] = val & 0xff;
1372 nic_state->regs.mult[7] = val & 0xff;
1378 rtl8139_tsd_write(dev, (port - RTL8139_TSD0)/4, val);
1384 nic_state->regs.tsad[(port - RTL8139_TSAD0)/4] = val;
1386 case RTL8139_RBSTART:
1387 nic_state->regs.rbstart = val;
1390 nic_state->regs.erbcr = val & 0xffff;
1393 //nic_state->regs.ersr = val & 0xff;
1394 nic_state->regs.ersr &= (~val) & 0x0c;
1397 rtl8139_cmd_write(dev, val);
1400 rtl8139_capr_write(dev, val & 0xffff);
1402 case RTL8139_CBR: //this is read only =====
1403 //nic_state->regs.cbr = val & 0xffff;
1406 rtl8139_imr_write(dev, val);
1409 rtl8139_isr_write(dev, val);
1412 nic_state->regs.tcr = val;
1415 rtl8139_rcr_write(dev, val);
1418 nic_state->regs.tctr = 0; //write clear current tick
1421 nic_state->regs.mpc = 0; //clear on write
1423 case RTL8139_9346CR:
1424 rtl8139_9346cr_write(dev, val);
1426 case RTL8139_CONFIG0:
1427 nic_state->regs.config[0] = val & 0xff;
1429 case RTL8139_CONFIG1:
1430 nic_state->regs.config[1] = val & 0xff;
1432 case RTL8139_TimerInt:
1433 nic_state->regs.timer_int = val;
1436 nic_state->regs.msr = val & 0xff;
1438 case RTL8139_CONFIG3:
1439 nic_state->regs.config3[0] = val & 0xff;
1441 case RTL8139_CONFIG4:
1442 nic_state->regs.config3[1] = val & 0xff;
1444 case RTL8139_MULINT:
1445 nic_state->regs.mulint = val & 0xffff;
1448 nic_state->regs.rerid = val & 0xffff;
1451 nic_state->regs.txsad = val & 0xffff;
1454 nic_state->regs.bmcr = val & 0xffff;
1457 nic_state->regs.bmsr = val & 0xffff;
1460 nic_state->regs.anar = val & 0xffff;
1462 case RTL8139_ANLPAR:
1463 nic_state->regs.anlpar = val & 0xffff;
1466 nic_state->regs.aner = val & 0xffff;
1469 nic_state->regs.dis = val & 0xffff;
1472 nic_state->regs.fcsc = val & 0xffff;
1474 case RTL8139_NWAYTR:
1475 nic_state->regs.nwaytr = val & 0xffff;
1478 nic_state->regs.rec = val & 0xffff;
1481 nic_state->regs.cscr = val;
1483 case RTL8139_PHY1_PARM:
1484 nic_state->regs.phy1_parm = val;
1486 case RTL8139_TW_PARM:
1487 nic_state->regs.tw_parm = val & 0xffff;
1489 case RTL8139_PHY2_PARM:
1490 nic_state->regs.phy2_parm = val;
1493 nic_state->regs.crc[0] = val & 0xff;
1496 nic_state->regs.crc[1] = val & 0xff;
1499 nic_state->regs.crc[2] = val & 0xff;
1502 nic_state->regs.crc[3] = val & 0xff;
1505 nic_state->regs.crc[4] = val & 0xff;
1508 nic_state->regs.crc[5] = val & 0xff;
1511 nic_state->regs.crc[6] = val & 0xff;
1514 nic_state->regs.crc[7] = val & 0xff;
1516 case RTL8139_Config5:
1517 nic_state->regs.config5 = val & 0xff;
1520 PrintDebug("rtl8139 write error: invalid port: 0x%x\n", port);
1524 #if TEST_PERFORMANCE
1525 if (need_hook(port, read))
1527 if (( ++io_total) % 50 == 0)
1528 PrintError("RTL8139: Total IO: %d, Hooked: %d, INT: %d\n", io_total, io_hooked, int_total);
1534 static int rtl8139_mmio_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data)
1538 struct vm_device *dev = (struct vm_device *)priv_data;
1539 struct nic_context *nic_state = (struct nic_context *)(dev->private_data);
1541 port = guest_addr & 0xff;
1545 val = nic_state->regs.id[0];
1548 val = nic_state->regs.id[1];
1551 val = nic_state->regs.id[2];
1554 val = nic_state->regs.id[3];
1557 val = nic_state->regs.id[4];
1560 val = nic_state->regs.id[5];
1563 val = nic_state->regs.mult[0];
1566 val = nic_state->regs.mult[1];
1569 val = nic_state->regs.mult[2];
1572 val = nic_state->regs.mult[3];
1575 val = nic_state->regs.mult[4];
1578 val = nic_state->regs.mult[5];
1581 val = nic_state->regs.mult[6];
1584 val = nic_state->regs.mult[7];
1587 val = nic_state->regs.tsd[0];
1590 val = nic_state->regs.tsd[1];
1593 val = nic_state->regs.tsd[2];
1596 val = nic_state->regs.tsd[3];
1599 val = nic_state->regs.tsad[0];
1602 val = nic_state->regs.tsad[1];
1605 val = nic_state->regs.tsad[2];
1608 val = nic_state->regs.tsad[3];
1610 case RTL8139_RBSTART:
1611 val = nic_state->regs.rbstart;
1614 val = nic_state->regs.erbcr;
1617 val = nic_state->regs.ersr;
1620 val = rtl8139_cmd_read(dev);
1623 val = rtl8139_capr_read(dev);
1626 val = nic_state->regs.cbr;
1629 val = nic_state->regs.imr;
1632 val = rtl8139_isr_read(dev);
1635 val = nic_state->regs.tcr;
1638 val = nic_state->regs.rcr;
1641 val = nic_state->regs.tctr;
1644 val = nic_state->regs.mpc;
1646 case RTL8139_9346CR:
1647 val = rtl8139_9346cr_read(dev);
1649 case RTL8139_CONFIG0:
1650 val = nic_state->regs.config[0];
1652 case RTL8139_CONFIG1:
1653 val = nic_state->regs.config[1];
1655 case RTL8139_TimerInt:
1656 val = nic_state->regs.timer_int;
1659 val = nic_state->regs.msr;
1661 case RTL8139_CONFIG3:
1662 val = nic_state->regs.config3[0];
1664 case RTL8139_CONFIG4:
1665 val = nic_state->regs.config3[1];
1667 case RTL8139_MULINT:
1668 val = nic_state->regs.mulint;
1671 val = nic_state->regs.rerid;
1674 val = rtl8139_tsad_read(dev);
1677 val = nic_state->regs.bmcr;
1680 val = nic_state->regs.bmsr;
1683 val = nic_state->regs.anar;
1685 case RTL8139_ANLPAR:
1686 val = nic_state->regs.anlpar;
1689 val = nic_state->regs.aner;
1692 val = nic_state->regs.dis;
1695 val = nic_state->regs.fcsc;
1697 case RTL8139_NWAYTR:
1698 val = nic_state->regs.nwaytr;
1701 val = nic_state->regs.rec;
1704 val = nic_state->regs.cscr;
1706 case RTL8139_PHY1_PARM:
1707 val = nic_state->regs.phy1_parm;
1709 case RTL8139_TW_PARM:
1710 val = nic_state->regs.tw_parm;
1712 case RTL8139_PHY2_PARM:
1713 val = nic_state->regs.phy2_parm;
1716 val = nic_state->regs.crc[0];
1719 val = nic_state->regs.crc[1];
1722 val = nic_state->regs.crc[2];
1725 val = nic_state->regs.crc[3];
1728 val = nic_state->regs.crc[4];
1731 val = nic_state->regs.crc[5];
1734 val = nic_state->regs.crc[6];
1737 val = nic_state->regs.crc[7];
1739 case RTL8139_Config5:
1740 val = nic_state->regs.config5;
1747 memcpy(dst, &val, length);
1749 PrintDebug("rtl8139 mmio read: port:0x%x (%u bytes): 0x%x\n", (int)guest_addr, length, val);
1751 #if TEST_PERFORMANCE
1752 if (need_hook(port, read))
1754 if (( ++io_total) % 50 == 0)
1755 PrintError("RTL8139: Total IO: %d, Hooked: %d, INT: %d\n", io_total, io_hooked, int_total);
1762 static int rtl8139_ioport_write(struct guest_info * core, uint16_t port, void *src, uint_t length, void * private_data)
1764 PrintDebug("rtl8139 pio write: port:0x%x (%u bytes)\n", port, length);
1766 rtl8139_mmio_write((addr_t)port, src, length, private_data);
1771 static int rtl8139_ioport_read(uint16_t port, void *dst, uint_t length, struct vm_device *dev)
1773 PrintDebug("rtl8139 pio read: port:0x%x (%u bytes)\n", port, length);
1775 rtl8139_mmio_read((addr_t)port, dst, length, (void *)dev);
1780 static int rtl8139_reset_device(struct vm_device *dev)
1782 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
1783 struct nic_regs *regs = &(nic_state->regs);
1784 regs->cmd |= CMD_Rst;
1786 regs->cmd &= ~CMD_Rst;
1790 static int rtl8139_start_device(struct vm_device *dev)
1792 PrintDebug("rtl8139: start device\n");
1793 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
1794 struct nic_regs *regs = &(nic_state->regs);
1795 regs->cmd |= CMD_Re | CMD_Te;
1799 static int rtl8139_stop_device(struct vm_device *dev)
1801 PrintDebug("rtl8139: stop device\n");
1802 struct nic_context *nic_state = (struct nic_context *)dev->private_data;
1803 struct nic_regs *regs = &(nic_state->regs);
1804 regs->cmd &= ~(CMD_Re | CMD_Te);
1808 static void init_phy_network()
1810 V3_REGISTER_PKT_DELIVERY(&netif_input);
1813 static int rtl8139_hook_iospace(struct vm_device *vmdev, addr_t base_addr, int size, int type, void *data)
1819 PrintError("In RTL8139: Fail to Hook IO Space, base address 0x%x\n", (int) base_addr);
1823 if (type == PCI_ADDRESS_SPACE_IO){
1824 PrintDebug("In RTL8139: Hook IO ports starting from %x, size %d\n", (int) base_addr, size);
1826 for (i = 0; i < 0xff; i++)
1828 v3_dev_hook_io(vmdev, base_addr + i, &rtl8139_ioport_read, &rtl8139_ioport_write);
1830 } else if (type == PCI_ADDRESS_SPACE_MEM) {
1831 PrintDebug("In RTL8139: Hook memory space starting from %x, size %d\n", (int) base_addr, size);
1833 //hook memory mapped I/O
1834 v3_hook_full_mem(vmdev->vm, base_addr, base_addr + 0xff,
1835 &rtl8139_mmio_read, &rtl8139_mmio_write, vmdev);
1837 PrintError("In RTL8139: unknown memory type: start %x, size %d\n", (int) base_addr, size);
1843 static int rtl8139_unhook_iospace()
1850 static struct pci_device * rtl8139_pci_init(struct vm_device *vmdev, struct pci_bus *bus, int devfn)
1853 struct pci_device *pdev;
1855 pdev = v3_pci_register_device(vmdev, bus, "REALTEK8139", devfn, NULL, NULL);
1859 PrintError("NIC: Register to PCI bus failed\n");
1863 pci_conf = pdev->configs;
1865 pci_conf[0x00] = 0xec;
1866 pci_conf[0x01] = 0x10;
1867 pci_conf[0x02] = 0x39;
1868 pci_conf[0x03] = 0x81;
1869 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
1870 pci_conf[0x08] = RTL8139_PCI_REVID_8139; /* PCI revision ID; >=0x20 is for 8139C+ */
1871 pci_conf[0x0a] = 0x00; // ethernet network controller
1872 pci_conf[0x0b] = 0x02;
1873 pci_conf[0x0e] = 0x00; // header_type
1874 pci_conf[0x3d] = 1; // interrupt pin 0
1875 pci_conf[0x3c] = 12;
1876 pci_conf[0x34] = 0xdc;
1878 pdev->vmdev = vmdev;
1880 v3_pci_register_io_region(pdev, 0, 0x100, PCI_ADDRESS_SPACE_IO, &rtl8139_hook_iospace);
1881 v3_pci_register_io_region(pdev, 1, 0x100, PCI_ADDRESS_SPACE_MEM, &rtl8139_hook_iospace);
1886 static int rtl8139_init_state(struct rtl8139_state *nic_state)
1888 PrintDebug("rtl8139: init_state\n");
1893 bus = v3_get_pcibus(dev->vm, 0);
1897 PrintDebug("Find PCI bus in guest, attach nic to the bus %p\n", bus);
1898 pdev = rtl8139_pci_init(dev, bus, -1);
1900 PrintError("Failure to attach nic to the bus %p\n", bus);
1903 nic_state->pci_dev = pdev;
1905 //rtl8139_hook_iospace(dev, 0x2000, 0x100, 1, NULL);
1910 static int rtl8139_deinit_device(struct vm_device *dev)
1913 rtl8139_unhook_iospace();
1918 static struct vm_device_ops dev_ops =
1920 .init = rtl8139_init_device,
1921 .deinit = rtl8139_deinit_device,
1922 .reset = rtl8139_reset_device,
1923 .start = rtl8139_start_device,
1924 .stop = rtl8139_stop_device,
1927 struct vm_device *v3_create_rtl8139()
1929 struct nic_context *nic_state = V3_Malloc(sizeof(struct nic_context));
1930 PrintDebug("rtl8139 internal at %p\n", (void *)nic_state);
1931 struct vm_device *dev = v3_create_device("RTL8139", &dev_ops, nic_state);
1937 static int register_dev(struct ne2k_state * nic_state)
1941 if (nic_state->pci_bus != NULL) {
1942 struct v3_pci_bar bars[6];
1943 struct pci_device * pci_dev = NULL;
1945 PrintDebug("NE2000: PCI Enabled\n");
1947 for (i = 0; i < 6; i++) {
1948 bars[i].type = PCI_BAR_NONE;
1951 bars[0].type = PCI_BAR_IO;
1952 bars[0].default_base_port = NIC_REG_BASE_PORT;
1953 bars[0].num_ports = 256;
1955 bars[0].io_read = ne2k_pci_read;
1956 bars[0].io_write = ne2k_pci_write;
1957 bars[0].private_data = nic_state;
1959 pci_dev = v3_pci_register_device(nic_state->pci_bus, PCI_STD_DEVICE, 0, -1, 0,
1961 pci_config_update, NULL, NULL, nic_state);
1964 if (pci_dev == NULL) {
1965 PrintError("NE2000: Could not register PCI Device\n");
1969 pci_dev->config_header.vendor_id = 0x10ec;
1970 pci_dev->config_header.device_id = 0x8029;
1971 pci_dev->config_header.revision = 0x00;
1973 pci_dev->config_header.subclass = 0x00;
1974 pci_dev->config_header.class = 0x02;
1975 pci_dev->config_header.header_type = 0x00;
1977 pci_dev->config_header.intr_line = 11;
1978 pci_dev->config_header.intr_pin = 1;
1980 nic_state->pci_dev = pci_dev;
1982 PrintDebug("NE2000: Not attached to PCI\n");
1984 v3_dev_hook_io(nic_state->dev, NIC_REG_BASE_PORT , &ne2k_cmd_read, &ne2k_cmd_write);
1986 for (i = 1; i < 16; i++){
1987 v3_dev_hook_io(nic_state->dev, NIC_REG_BASE_PORT + i, &ne2k_std_read, &ne2k_std_write);
1990 v3_dev_hook_io(nic_state->dev, NIC_DATA_PORT, &ne2k_data_read, &ne2k_data_write);
1991 v3_dev_hook_io(nic_state->dev, NIC_RESET_PORT, &ne2k_reset_port_read, &ne2k_reset_port_write);
1998 static int connect_fn(struct v3_vm_info * info,
1999 void * frontend_data,
2000 struct v3_dev_net_ops * ops,
2001 v3_cfg_tree_t * cfg,
2002 void * private_data) {
2003 struct ne2k_state * nic_state = (struct ne2k_state *)frontend_data;
2005 rtl8139_init_state(nic_state);
2006 register_dev(nic_state);
2008 nic_state->net_ops = ops;
2009 nic_state->backend_data = private_data;
2011 ops->recv = ne2k_rx;
2013 ops->start_tx = NULL;
2014 ops->stop_tx = NULL;
2015 ops->frontend_data = nic_state;
2016 memcpy(ops->fnt_mac, nic_state->mac, ETH_ALEN);
2022 static int rtl8139_free(struct ne2k_state * nic_state) {
2025 /* dettached from backend */
2027 if(nic_state->pci_bus == NULL){
2028 for (i = 0; i < 16; i++){
2029 v3_dev_unhook_io(nic_state->dev, NIC_REG_BASE_PORT + i);
2032 v3_dev_unhook_io(nic_state->dev, NIC_DATA_PORT);
2033 v3_dev_unhook_io(nic_state->dev, NIC_RESET_PORT);
2035 /* unregistered from PCI? */
2046 static struct v3_device_ops dev_ops = {
2047 .free = (int (*)(void *))rtl8139_free,
2051 static int rtl8139_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
2052 struct vm_device * pci_bus = v3_find_dev(vm, v3_cfg_val(cfg, "bus"));
2053 struct rtl8139_state * nic_state = NULL;
2054 char * dev_id = v3_cfg_val(cfg, "ID");
2055 char * macstr = v3_cfg_val(cfg, "mac");
2057 nic_state = (struct rtl8139_state *)V3_Malloc(sizeof(struct rtl8139_state));
2058 memset(nic_state, 0, sizeof(struct ne2k_state));
2060 nic_state->pci_bus = pci_bus;
2063 if (macstr != NULL && !str2mac(macstr, nic_state->mac)) {
2064 PrintDebug("RTL8139: Mac specified %s\n", macstr);
2066 PrintDebug("RTL8139: MAC not specified\n");
2067 random_ethaddr(nic_state->mac);
2070 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, nic_state);
2073 PrintError("RTL8139: Could not attach device %s\n", dev_id);
2078 nic_state->dev = dev;
2080 if (v3_dev_add_net_frontend(vm, dev_id, connect_fn, (void *)nic_state) == -1) {
2081 PrintError("RTL8139: Could not register %s as net frontend\n", dev_id);
2082 v3_remove_device(dev);
2090 device_register("RTL8139", rtl8139_init)