2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
12 * Copyright (c) 2009, Jack Lange <jarusl@cs.northwestern.edu>
13 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Lei Xia <lxia@northwestern.edu>
17 * Chang Seok Bae <jhuell@gmail.com>
18 * Jack Lange <jarusl@cs.northwestern.edu>
20 * This is free software. You are permitted to use,
21 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
26 #include <palacios/vmm.h>
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_io.h>
29 #include <palacios/vmm_intr.h>
30 #include <palacios/vmm_rbtree.h>
32 #include <devices/pci.h>
33 #include <devices/pci_types.h>
37 #define PrintDebug(fmt, args...)
41 #define CONFIG_ADDR_PORT 0x0cf8
42 #define CONFIG_DATA_PORT 0x0cfc
45 #define PCI_BUS_COUNT 1
47 // This must always be a multiple of 8
48 #define MAX_BUS_DEVICES 32
61 } __attribute__((packed));
62 } __attribute__((packed));
63 } __attribute__((packed));
72 // Red Black tree containing all attached devices
73 struct rb_root devices;
75 // Bitmap of the allocated device numbers
76 uint8_t dev_map[MAX_BUS_DEVICES / 8];
82 // Configuration address register
83 struct pci_addr_reg addr_reg;
86 struct pci_bus bus_list[PCI_BUS_COUNT];
95 static void pci_dump_state(struct pci_internal * pci_state) {
96 struct rb_node * node = v3_rb_first(&(pci_state->bus_list[0].devices));
97 struct pci_device * tmp_dev = NULL;
99 PrintDebug("===PCI: Dumping state Begin ==========\n");
102 tmp_dev = rb_entry(node, struct pci_device, dev_tree_node);
104 PrintDebug("PCI Device Number: %d (%s):\n", tmp_dev->dev_num, tmp_dev->name);
105 PrintDebug("irq = %d\n", tmp_dev->config_header.intr_line);
106 PrintDebug("Vend ID: 0x%x\n", tmp_dev->config_header.vendor_id);
107 PrintDebug("Device ID: 0x%x\n", tmp_dev->config_header.device_id);
109 } while ((node = v3_rb_next(node)));
111 PrintDebug("====PCI: Dumping state End==========\n");
119 // Scan the dev_map bitmap for the first '0' bit
120 static int get_free_dev_num(struct pci_bus * bus) {
123 for (i = 0; i < sizeof(bus->dev_map); i++) {
124 PrintDebug("i=%d\n", i);
125 if (bus->dev_map[i] != 0xff) {
127 for (j = 0; j < 8; j++) {
128 PrintDebug("\tj=%d\n", j);
129 if (!(bus->dev_map[i] & (0x1 << j))) {
130 return ((i * 8) + j);
139 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
140 int major = (dev_num / 8);
141 int minor = dev_num % 8;
143 bus->dev_map[major] |= (0x1 << minor);
149 struct pci_device * __add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
151 struct rb_node ** p = &(bus->devices.rb_node);
152 struct rb_node * parent = NULL;
153 struct pci_device * tmp_dev = NULL;
157 tmp_dev = rb_entry(parent, struct pci_device, dev_tree_node);
159 if (dev->devfn < tmp_dev->devfn) {
161 } else if (dev->devfn > tmp_dev->devfn) {
168 rb_link_node(&(dev->dev_tree_node), parent, p);
175 struct pci_device * add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
177 struct pci_device * ret = NULL;
179 if ((ret = __add_device_to_bus(bus, dev))) {
183 v3_rb_insert_color(&(dev->dev_tree_node), &(bus->devices));
185 allocate_dev_num(bus, dev->dev_num);
191 static struct pci_device * get_device(struct pci_bus * bus, uint8_t dev_num, uint8_t fn_num) {
192 struct rb_node * n = bus->devices.rb_node;
193 struct pci_device * dev = NULL;
194 uint8_t devfn = ((dev_num & 0x1f) << 3) | (fn_num & 0x7);
197 dev = rb_entry(n, struct pci_device, dev_tree_node);
199 if (devfn < dev->devfn) {
201 } else if (devfn > dev->devfn) {
217 static int addr_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
218 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
219 int reg_offset = port & 0x3;
220 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
222 PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
225 if (reg_offset != 0) {
226 PrintError("Invalid Address Port Read\n");
229 *(uint32_t *)dst = *(uint32_t *)reg_addr;
230 } else if (length == 2) {
231 if (reg_offset > 2) {
232 PrintError("Invalid Address Port Read\n");
235 *(uint16_t *)dst = *(uint16_t *)reg_addr;
236 } else if (length == 1) {
237 *(uint8_t *)dst = *(uint8_t *)reg_addr;
239 PrintError("Invalid read length (%d) for PCI address register\n", length);
248 static int addr_port_write(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
249 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
250 int reg_offset = port & 0x3;
251 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
255 if (reg_offset != 0) {
256 PrintError("Invalid Address Port Write\n");
260 PrintDebug("Writing PCI 4 bytes Val=%x\n", *(uint32_t *)src);
262 *(uint32_t *)reg_addr = *(uint32_t *)src;
263 } else if (length == 2) {
264 if (reg_offset > 2) {
265 PrintError("Invalid Address Port Write\n");
269 PrintDebug("Writing PCI 2 byte Val=%x\n", *(uint16_t *)src);
271 *(uint16_t *)reg_addr = *(uint16_t *)src;
272 } else if (length == 1) {
273 PrintDebug("Writing PCI 1 byte Val=%x\n", *(uint8_t *)src);
274 *(uint8_t *)reg_addr = *(uint8_t *)src;
276 PrintError("Invalid write length (%d) for PCI address register\n", length);
280 PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
286 static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * vmdev) {
287 struct pci_internal * pci_state = (struct pci_internal *)(vmdev->private_data);
288 struct pci_device * pci_dev = NULL;
289 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
292 if (pci_state->addr_reg.bus_num != 0) {
294 for (i = 0; i < length; i++) {
295 *((uint8_t *)dst + i) = 0xff;
301 PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n",
302 pci_state->addr_reg.bus_num,
303 pci_state->addr_reg.dev_num,
305 pci_state->addr_reg.val);
307 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
309 if (pci_dev == NULL) {
310 for (i = 0; i < length; i++) {
311 *(uint8_t *)((uint8_t *)dst + i) = 0xff;
317 for (i = 0; i < length; i++) {
318 *(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
321 PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
327 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
328 if (header_type == 0x00) {
346 } else if (header_type == 0x80) {
365 // PCI to PCI Bridge = 0x01
366 // CardBus Bridge = 0x02
369 PrintError("Invalid PCI Header type (0x%.2x)\n", header_type);
376 static int bar_update(struct pci_device * pci, int bar_num, uint32_t new_val) {
377 struct v3_pci_bar * bar = &(pci->bar[bar_num]);
379 PrintDebug("Updating BAR Register (Dev=%s) (bar=%d) (old_val=%x) (new_val=%x)\n",
380 pci->name, bar_num, bar->val, new_val);
386 PrintDebug("\tRehooking %d IO ports from base %x to %x\n",
387 bar->num_ports, PCI_IO_BASE(bar->val), PCI_IO_BASE(new_val));
389 // only do this if pci device is enabled....
390 for (i = 0; i < bar->num_ports; i++) {
392 v3_dev_unhook_io(pci->vm_dev, PCI_IO_BASE(bar->val) + i);
394 v3_dev_hook_io(pci->vm_dev, PCI_IO_BASE(new_val) + i,
395 bar->io_read, bar->io_write);
402 case PCI_BAR_MEM32: {
403 v3_unhook_mem(pci->vm_dev->vm, (addr_t)(bar->val));
406 v3_hook_full_mem(pci->vm_dev->vm, PCI_MEM32_BASE(new_val),
407 PCI_MEM32_BASE(new_val) + (bar->num_pages * PAGE_SIZE_4KB),
408 bar->mem_read, bar->mem_write, pci->vm_dev);
410 PrintError("Write hooks not supported for PCI\n");
419 PrintDebug("Reprogramming an unsupported BAR register (Dev=%s) (bar=%d) (val=%x)\n",
420 pci->name, bar_num, new_val);
424 PrintError("Invalid Bar Reg updated (bar=%d)\n", bar_num);
432 static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_device * vmdev) {
433 struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;
434 struct pci_device * pci_dev = NULL;
435 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
439 if (pci_state->addr_reg.bus_num != 0) {
443 PrintDebug("Writing PCI Data register. bus = %d, dev = %d, reg = %d (%x) addr_reg = %x (val=%x, len=%d)\n",
444 pci_state->addr_reg.bus_num,
445 pci_state->addr_reg.dev_num,
447 pci_state->addr_reg.val,
448 *(uint32_t *)src, length);
451 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
453 if (pci_dev == NULL) {
454 PrintError("Writing configuration space for non-present device (dev_num=%d)\n",
455 pci_state->addr_reg.dev_num);
460 for (i = 0; i < length; i++) {
461 uint_t cur_reg = reg_num + i;
462 int writable = is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg);
464 if (writable == -1) {
465 PrintError("Invalid PCI configuration space\n");
470 pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
472 if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
473 // BAR Register Update
474 int bar_reg = ((cur_reg & ~0x3) - 0x10) / 4;
476 pci_dev->bar_update_flag = 1;
477 pci_dev->bar[bar_reg].updated = 1;
479 // PrintDebug("Updating BAR register %d\n", bar_reg);
481 } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
482 // Extension ROM update
484 pci_dev->ext_rom_update_flag = 1;
485 } else if (cur_reg == 0x04) {
487 uint8_t command = *((uint8_t *)src + i);
489 PrintError("command update for %s old=%x new=%x\n",
491 pci_dev->config_space[cur_reg],command);
493 pci_dev->config_space[cur_reg] = command;
495 if (pci_dev->cmd_update) {
496 pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
499 } else if (cur_reg == 0x0f) {
501 pci_dev->config_header.BIST = 0x00;
506 if (pci_dev->config_update) {
507 pci_dev->config_update(pci_dev, reg_num, length);
510 // Scan for BAR updated
511 if (pci_dev->bar_update_flag) {
512 for (i = 0; i < 6; i++) {
513 if (pci_dev->bar[i].updated) {
514 int bar_offset = 0x10 + 4 * i;
516 *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
517 // check special flags....
520 if (bar_update(pci_dev, i, *(uint32_t *)(pci_dev->config_space + bar_offset)) == -1) {
521 PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
525 pci_dev->bar[i].updated = 0;
528 pci_dev->bar_update_flag = 0;
531 if ((pci_dev->ext_rom_update_flag) && (pci_dev->ext_rom_update)) {
532 pci_dev->ext_rom_update(pci_dev);
533 pci_dev->ext_rom_update_flag = 0;
542 static int pci_reset_device(struct vm_device * dev) {
543 PrintDebug("pci: reset device\n");
548 static int pci_start_device(struct vm_device * dev) {
549 PrintDebug("pci: start device\n");
554 static int pci_stop_device(struct vm_device * dev) {
555 PrintDebug("pci: stop device\n");
561 static int pci_free(struct vm_device * dev) {
564 for (i = 0; i < 4; i++){
565 v3_dev_unhook_io(dev, CONFIG_ADDR_PORT + i);
566 v3_dev_unhook_io(dev, CONFIG_DATA_PORT + i);
574 static void init_pci_busses(struct pci_internal * pci_state) {
577 for (i = 0; i < PCI_BUS_COUNT; i++) {
578 pci_state->bus_list[i].bus_num = i;
579 pci_state->bus_list[i].devices.rb_node = NULL;
580 memset(pci_state->bus_list[i].dev_map, 0, sizeof(pci_state->bus_list[i].dev_map));
587 static struct v3_device_ops dev_ops = {
589 .reset = pci_reset_device,
590 .start = pci_start_device,
591 .stop = pci_stop_device,
597 static int pci_init(struct guest_info * vm, void * cfg_data) {
598 struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
601 PrintDebug("PCI internal at %p\n",(void *)pci_state);
603 struct vm_device * dev = v3_allocate_device("PCI", &dev_ops, pci_state);
605 if (v3_attach_device(vm, dev) == -1) {
606 PrintError("Could not attach device %s\n", "PCI");
611 pci_state->addr_reg.val = 0;
613 init_pci_busses(pci_state);
615 PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
617 for (i = 0; i < 4; i++) {
618 v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
619 v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
626 device_register("PCI", pci_init)
629 static inline int init_bars(struct pci_device * pci_dev) {
632 for (i = 0; i < 6; i++) {
633 int bar_offset = 0x10 + (4 * i);
635 if (pci_dev->bar[i].type == PCI_BAR_IO) {
637 pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
639 pci_dev->bar[i].val = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
640 pci_dev->bar[i].val |= 0x00000001;
642 for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
644 if (pci_dev->bar[i].default_base_port != 0xffff) {
645 if (v3_dev_hook_io(pci_dev->vm_dev, pci_dev->bar[i].default_base_port + j,
646 pci_dev->bar[i].io_read, pci_dev->bar[i].io_write) == -1) {
647 PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
653 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
655 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
656 pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
657 pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
659 pci_dev->bar[i].val = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
662 if (pci_dev->bar[i].mem_read) {
664 v3_hook_full_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
665 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
666 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->vm_dev);
667 } else if (pci_dev->bar[i].mem_write) {
669 PrintError("Write hooks not supported for PCI devices\n");
672 v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
673 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
674 pci_dev->bar[i].mem_write, pci_dev->vm_dev);
677 // set the prefetchable flag...
678 pci_dev->bar[i].val |= 0x00000008;
682 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
684 } else if (pci_dev->bar[i].type == PCI_BAR_MEM16) {
685 PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
687 } else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
688 pci_dev->bar[i].val = 0x00000000;
689 pci_dev->bar[i].mask = 0x00000000; // This ensures that all updates will be dropped
690 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
692 PrintError("Invalid BAR type for bar #%d\n", i);
701 // if dev_num == -1, auto assign
702 struct pci_device * v3_pci_register_device(struct vm_device * pci,
703 pci_device_type_t dev_type,
708 struct v3_pci_bar * bars,
709 int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
710 int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
711 int (*ext_rom_update)(struct pci_device * pci_dev),
712 struct vm_device * dev) {
714 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
715 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
716 struct pci_device * pci_dev = NULL;
719 if (dev_num > MAX_BUS_DEVICES) {
720 PrintError("Requested Invalid device number (%d)\n", dev_num);
724 if (dev_num == PCI_AUTO_DEV_NUM) {
725 PrintDebug("Searching for free device number\n");
726 if ((dev_num = get_free_dev_num(bus)) == -1) {
727 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
732 PrintDebug("Checking for PCI Device\n");
734 if (get_device(bus, dev_num, fn_num) != NULL) {
735 PrintError("PCI Device already registered at slot %d on bus %d\n",
736 dev_num, bus->bus_num);
741 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
743 if (pci_dev == NULL) {
744 PrintError("Could not allocate pci device\n");
748 memset(pci_dev, 0, sizeof(struct pci_device));
753 pci_dev->config_header.header_type = 0x00;
755 case PCI_MULTIFUNCTION:
756 pci_dev->config_header.header_type = 0x80;
759 PrintError("Unhandled PCI Device Type: %d\n", dev_type);
763 pci_dev->bus_num = bus_num;
764 pci_dev->dev_num = dev_num;
765 pci_dev->fn_num = fn_num;
767 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
768 pci_dev->vm_dev = dev;
770 // register update callbacks
771 pci_dev->config_update = config_update;
772 pci_dev->cmd_update = cmd_update;
773 pci_dev->ext_rom_update = ext_rom_update;
777 for (i = 0; i < 6; i ++) {
778 pci_dev->bar[i].type = bars[i].type;
780 if (pci_dev->bar[i].type == PCI_BAR_IO) {
781 pci_dev->bar[i].num_ports = bars[i].num_ports;
782 pci_dev->bar[i].default_base_port = bars[i].default_base_port;
783 pci_dev->bar[i].io_read = bars[i].io_read;
784 pci_dev->bar[i].io_write = bars[i].io_write;
785 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
786 pci_dev->bar[i].num_pages = bars[i].num_pages;
787 pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
788 pci_dev->bar[i].mem_read = bars[i].mem_read;
789 pci_dev->bar[i].mem_write = bars[i].mem_write;
791 pci_dev->bar[i].num_pages = 0;
792 pci_dev->bar[i].default_base_addr = 0;
793 pci_dev->bar[i].mem_read = NULL;
794 pci_dev->bar[i].mem_write = NULL;
798 if (init_bars(pci_dev) == -1) {
799 PrintError("could not initialize bar registers\n");
804 add_device_to_bus(bus, pci_dev);
807 pci_dump_state(pci_state);