palacios/src/devices/ide.c

   1 /*
   2  * This file is part of the Palacios Virtual Machine Monitor developed
   3  * by the V3VEE Project with funding from the United States National
   4  * Science Foundation and the Department of Energy.
   5  *
   6  * The V3VEE Project is a joint project between Northwestern University
   7  * and the University of New Mexico.  You can find out more at
   8  * http://www.v3vee.org
   9  *
  10  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
  11  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
  12  * All rights reserved.
  13  *
  14  * Author: Jack Lange <jarusl@cs.northwestern.edu>
  15  *
  16  * This is free software.  You are permitted to use,
  17  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
  18  */
  19
  20 #include <palacios/vmm.h>
  21 #include <palacios/vm_guest_mem.h>
  22 #include <devices/ide.h>
  23 #include <devices/pci.h>
  24 #include "ide-types.h"
  25 #include "atapi-types.h"
  26
  27 #ifndef DEBUG_IDE
  28 #undef PrintDebug
  29 #define PrintDebug(fmt, args...)
  30 #endif
  31
  32 #define PRI_DEFAULT_IRQ 14
  33 #define SEC_DEFAULT_IRQ 15
  34
  35
  36 #define PRI_DATA_PORT         0x1f0
  37 #define PRI_FEATURES_PORT     0x1f1
  38 #define PRI_SECT_CNT_PORT     0x1f2
  39 #define PRI_SECT_NUM_PORT     0x1f3
  40 #define PRI_CYL_LOW_PORT      0x1f4
  41 #define PRI_CYL_HIGH_PORT     0x1f5
  42 #define PRI_DRV_SEL_PORT      0x1f6
  43 #define PRI_CMD_PORT          0x1f7
  44 #define PRI_CTRL_PORT         0x3f6
  45 #define PRI_ADDR_REG_PORT     0x3f7
  46
  47 #define SEC_DATA_PORT         0x170
  48 #define SEC_FEATURES_PORT     0x171
  49 #define SEC_SECT_CNT_PORT     0x172
  50 #define SEC_SECT_NUM_PORT     0x173
  51 #define SEC_CYL_LOW_PORT      0x174
  52 #define SEC_CYL_HIGH_PORT     0x175
  53 #define SEC_DRV_SEL_PORT      0x176
  54 #define SEC_CMD_PORT          0x177
  55 #define SEC_CTRL_PORT         0x376
  56 #define SEC_ADDR_REG_PORT     0x377
  57
  58
  59 #define PRI_DEFAULT_DMA_PORT 0xc000
  60 #define SEC_DEFAULT_DMA_PORT 0xc008
  61
  62 #define DATA_BUFFER_SIZE 2048
  63
  64 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
  65                                           "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
  66                                            "PRI_CTRL", "PRI_ADDR_REG"};
  67
  68
  69 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
  70                                           "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
  71                                            "SEC_CTRL", "SEC_ADDR_REG"};
  72
  73 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
  74                                            "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
  75
  76
  77
  78 static inline const char * io_port_to_str(uint16_t port) {
  79     if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
  80         return ide_pri_port_strs[port - PRI_DATA_PORT];
  81     } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
  82         return ide_sec_port_strs[port - SEC_DATA_PORT];
  83     } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
  84         return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
  85     } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
  86         return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
  87     }
  88     return NULL;
  89 }
  90
  91
  92 static inline const char * dma_port_to_str(uint16_t port) {
  93     return ide_dma_port_strs[port & 0x7];
  94 }
  95
  96
  97 static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" };
  98
  99
 100 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
 101     if (type > 2) {
 102         return NULL;
 103     }
 104
 105     return ide_dev_type_strs[type];
 106 }
 107
 108
 109
 110 struct ide_cd_state {
 111     struct atapi_sense_data sense;
 112
 113     uint8_t atapi_cmd;
 114     struct atapi_error_recovery err_recovery;
 115 };
 116
 117 struct ide_hd_state {
 118     int accessed;
 119
 120     /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
 121     uint_t mult_sector_num;
 122
 123     /* This is the current op sector size:
 124      * for multiple sector ops this equals mult_sector_num
 125      * for standard ops this equals 1
 126      */
 127     uint_t cur_sector_num;
 128 };
 129
 130 struct ide_drive {
 131     // Command Registers
 132
 133     v3_ide_dev_type_t drive_type;
 134
 135     union {
 136         struct v3_ide_cd_ops * cd_ops;
 137         struct v3_ide_hd_ops * hd_ops;
 138     };
 139
 140
 141     union {
 142         struct ide_cd_state cd_state;
 143         struct ide_hd_state hd_state;
 144     };
 145
 146     char model[41];
 147
 148     // Where we are in the data transfer
 149     uint_t transfer_index;
 150
 151     // the length of a transfer
 152     // calculated for easy access
 153     uint_t transfer_length;
 154
 155     uint64_t current_lba;
 156
 157     // We have a local data buffer that we use for IO port accesses
 158     uint8_t data_buf[DATA_BUFFER_SIZE];
 159
 160
 161     void * private_data;
 162
 163     union {
 164         uint8_t sector_count;             // 0x1f2,0x172
 165         struct atapi_irq_flags irq_flags;
 166     } __attribute__((packed));
 167
 168     union {
 169         uint8_t sector_num;               // 0x1f3,0x173
 170         uint8_t lba0;
 171     } __attribute__((packed));
 172
 173     union {
 174         uint16_t cylinder;
 175         uint16_t lba12;
 176
 177         struct {
 178             uint8_t cylinder_low;       // 0x1f4,0x174
 179             uint8_t cylinder_high;      // 0x1f5,0x175
 180         } __attribute__((packed));
 181
 182         struct {
 183             uint8_t lba1;
 184             uint8_t lba2;
 185         } __attribute__((packed));
 186
 187
 188         // The transfer length requested by the CPU
 189         uint16_t req_len;
 190     } __attribute__((packed));
 191
 192 };
 193
 194
 195
 196 struct ide_channel {
 197     struct ide_drive drives[2];
 198
 199     // Command Registers
 200     struct ide_error_reg error_reg;     // [read] 0x1f1,0x171
 201
 202     struct ide_features_reg features;
 203
 204     struct ide_drive_head_reg drive_head; // 0x1f6,0x176
 205
 206     struct ide_status_reg status;       // [read] 0x1f7,0x177
 207     uint8_t cmd_reg;                // [write] 0x1f7,0x177
 208
 209     int irq; // this is temporary until we add PCI support
 210
 211     struct pci_device * pci_dev;
 212
 213     // Control Registers
 214     struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
 215
 216     struct ide_dma_cmd_reg dma_cmd;
 217     struct ide_dma_status_reg dma_status;
 218     uint32_t dma_prd_addr;
 219     uint_t dma_tbl_index;
 220 };
 221
 222
 223
 224 struct ide_internal {
 225     struct ide_channel channels[2];
 226     struct vm_device * pci;
 227     struct vm_device * southbridge;
 228     struct pci_device * busmaster_pci;
 229 };
 230
 231
 232
 233
 234
 235 /* Utility functions */
 236
 237 static inline uint16_t be_to_le_16(const uint16_t val) {
 238     uint8_t * buf = (uint8_t *)&val;
 239     return (buf[0] << 8) | (buf[1]) ;
 240 }
 241
 242 static inline uint16_t le_to_be_16(const uint16_t val) {
 243     return be_to_le_16(val);
 244 }
 245
 246
 247 static inline uint32_t be_to_le_32(const uint32_t val) {
 248     uint8_t * buf = (uint8_t *)&val;
 249     return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
 250 }
 251
 252 static inline uint32_t le_to_be_32(const uint32_t val) {
 253     return be_to_le_32(val);
 254 }
 255
 256
 257 static inline int get_channel_index(ushort_t port) {
 258     if (((port & 0xfff8) == 0x1f0) ||
 259         ((port & 0xfffe) == 0x3f6) ||
 260         ((port & 0xfff8) == 0xc000)) {
 261         return 0;
 262     } else if (((port & 0xfff8) == 0x170) ||
 263                ((port & 0xfffe) == 0x376) ||
 264                ((port & 0xfff8) == 0xc008)) {
 265         return 1;
 266     }
 267
 268     return -1;
 269 }
 270
 271 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
 272     int channel_idx = get_channel_index(port);
 273     return &(ide->channels[channel_idx]);
 274 }
 275
 276 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
 277     return &(channel->drives[channel->drive_head.drive_sel]);
 278 }
 279
 280
 281 static inline int is_lba_enabled(struct ide_channel * channel) {
 282     return channel->drive_head.lba_mode;
 283 }
 284
 285
 286 /* Drive Commands */
 287 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
 288     if (channel->ctrl_reg.irq_disable == 0) {
 289         PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
 290         channel->dma_status.int_gen = 1;
 291         v3_raise_irq(dev->vm, channel->irq);
 292     }
 293 }
 294
 295
 296 static void drive_reset(struct ide_drive * drive) {
 297     drive->sector_count = 0x01;
 298     drive->sector_num = 0x01;
 299
 300     PrintDebug("Resetting drive %s\n", drive->model);
 301
 302     if (drive->drive_type == IDE_CDROM) {
 303         drive->cylinder = 0xeb14;
 304     } else {
 305         drive->cylinder = 0x0000;
 306         //drive->hd_state.accessed = 0;
 307     }
 308
 309
 310     memset(drive->data_buf, 0, sizeof(drive->data_buf));
 311     drive->transfer_index = 0;
 312
 313     // Send the reset signal to the connected device callbacks
 314     //     channel->drives[0].reset();
 315     //    channel->drives[1].reset();
 316 }
 317
 318 static void channel_reset(struct ide_channel * channel) {
 319
 320     // set busy and seek complete flags
 321     channel->status.val = 0x90;
 322
 323     // Clear errors
 324     channel->error_reg.val = 0x01;
 325
 326     // clear commands
 327     channel->cmd_reg = 0x00;
 328
 329     channel->ctrl_reg.irq_disable = 0;
 330 }
 331
 332 static void channel_reset_complete(struct ide_channel * channel) {
 333     channel->status.busy = 0;
 334     channel->status.ready = 1;
 335
 336     channel->drive_head.head_num = 0;
 337
 338     drive_reset(&(channel->drives[0]));
 339     drive_reset(&(channel->drives[1]));
 340 }
 341
 342
 343 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
 344     channel->status.val = 0x41; // Error + ready
 345     channel->error_reg.val = 0x04; // No idea...
 346
 347     ide_raise_irq(dev, channel);
 348 }
 349
 350
 351
 352
 353
 354
 355 /* ATAPI functions */
 356 #include "atapi.h"
 357
 358 /* ATA functions */
 359 #include "ata.h"
 360
 361
 362
 363 /* IO Operations */
 364 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
 365     struct ide_drive * drive = get_selected_drive(channel);
 366     struct ide_dma_prd prd_entry;
 367     uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
 368     int ret;
 369
 370     PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
 371
 372     ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
 373
 374     if (ret != sizeof(struct ide_dma_prd)) {
 375         PrintError("Could not read PRD\n");
 376         return -1;
 377     }
 378
 379     PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
 380
 381     ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf);
 382
 383     if (ret != prd_entry.size) {
 384         PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
 385         return -1;
 386     }
 387
 388
 389
 390     /*
 391       drive->irq_flags.io_dir = 1;
 392       drive->irq_flags.c_d = 1;
 393       drive->irq_flags.rel = 0;
 394     */
 395
 396
 397     // set DMA status
 398
 399     if (prd_entry.end_of_table) {
 400         channel->dma_status.active = 0;
 401         channel->dma_status.err = 0;
 402         channel->dma_status.int_gen = 1;
 403
 404         channel->status.busy = 0;
 405         channel->status.ready = 1;
 406         channel->status.data_req = 0;
 407         channel->status.error = 0;
 408         channel->status.seek_complete = 1;
 409     }
 410
 411     ide_raise_irq(dev, channel);
 412
 413     return 0;
 414 }
 415
 416
 417 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
 418     // unsupported
 419     PrintError("DMA writes currently not supported\n");
 420     return -1;
 421 }
 422
 423
 424 /*
 425  * This is an ugly ugly ugly way to differentiate between the first and second DMA channels
 426  */
 427
 428 static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel);
 429 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel);
 430
 431
 432 static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
 433     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 434     PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
 435     return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0]));
 436 }
 437
 438 static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
 439     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 440     PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
 441     return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1]));
 442 }
 443
 444
 445 static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
 446     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 447     PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
 448     return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0]));
 449 }
 450
 451 static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
 452     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 453     PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
 454     return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1]));
 455 }
 456
 457
 458 #define DMA_CMD_PORT      0x00
 459 #define DMA_STATUS_PORT   0x02
 460 #define DMA_PRD_PORT0     0x04
 461 #define DMA_PRD_PORT1     0x05
 462 #define DMA_PRD_PORT2     0x06
 463 #define DMA_PRD_PORT3     0x07
 464
 465
 466 static int write_dma_port(ushort_t port_offset, void * src, uint_t length,
 467                           struct vm_device * dev, struct ide_channel * channel) {
 468
 469     switch (port_offset) {
 470         case DMA_CMD_PORT:
 471             channel->dma_cmd.val = *(uint8_t *)src;
 472
 473             if (channel->dma_cmd.start == 0) {
 474                 channel->dma_tbl_index = 0;
 475             } else {
 476                 channel->dma_status.active = 1;
 477
 478                 if (channel->dma_cmd.read == 1) {
 479                     // DMA Read
 480                     if (dma_read(dev, channel) == -1) {
 481                         PrintError("Failed DMA Read\n");
 482                         return -1;
 483                     }
 484                 } else {
 485                     // DMA write
 486                     if (dma_write(dev, channel) == -1) {
 487                         PrintError("Failed DMA Write\n");
 488                         return -1;
 489                     }
 490                 }
 491
 492                 channel->dma_cmd.val &= 0x09;
 493             }
 494
 495             break;
 496
 497         case DMA_STATUS_PORT:
 498             if (length != 1) {
 499                 PrintError("Invalid read length for DMA status port\n");
 500                 return -1;
 501             }
 502
 503             channel->dma_status.val = *(uint8_t *)src;
 504             break;
 505
 506         case DMA_PRD_PORT0:
 507         case DMA_PRD_PORT1:
 508         case DMA_PRD_PORT2:
 509         case DMA_PRD_PORT3: {
 510             uint_t addr_index = port_offset & 0x3;
 511             uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
 512             int i = 0;
 513
 514             if (addr_index + length > 4) {
 515                 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
 516                 return -1;
 517             }
 518
 519             for (i = 0; i < length; i++) {
 520                 addr_buf[addr_index + i] = *((uint8_t *)src + i);
 521             }
 522
 523             PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
 524
 525             break;
 526         }
 527         default:
 528             PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
 529             return -1;
 530     }
 531
 532     return length;
 533 }
 534
 535
 536 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length,
 537                          struct vm_device * dev, struct ide_channel * channel) {
 538
 539     switch (port_offset) {
 540         case DMA_CMD_PORT:
 541             *(uint8_t *)dst = channel->dma_cmd.val;
 542             break;
 543
 544         case DMA_STATUS_PORT:
 545             if (length != 1) {
 546                 PrintError("Invalid read length for DMA status port\n");
 547                 return -1;
 548             }
 549
 550             *(uint8_t *)dst = channel->dma_status.val;
 551             break;
 552
 553         case DMA_PRD_PORT0:
 554         case DMA_PRD_PORT1:
 555         case DMA_PRD_PORT2:
 556         case DMA_PRD_PORT3: {
 557             uint_t addr_index = port_offset & 0x3;
 558             uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
 559             int i = 0;
 560
 561             if (addr_index + length > 4) {
 562                 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
 563                 return -1;
 564             }
 565
 566             for (i = 0; i < length; i++) {
 567                 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
 568             }
 569
 570             break;
 571         }
 572         default:
 573             PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
 574             return -1;
 575     }
 576
 577     PrintDebug("\tval=%x\n", *(uint32_t *)dst);
 578
 579     return length;
 580 }
 581
 582
 583
 584 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
 585     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 586     struct ide_channel * channel = get_selected_channel(ide, port);
 587     struct ide_drive * drive = get_selected_drive(channel);
 588
 589     if (length != 1) {
 590         PrintError("Invalid Write Length on IDE command Port %x\n", port);
 591         return -1;
 592     }
 593
 594     PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
 595
 596     channel->cmd_reg = *(uint8_t *)src;
 597
 598     switch (channel->cmd_reg) {
 599
 600         case 0xa1: // ATAPI Identify Device Packet
 601             if (drive->drive_type != IDE_CDROM) {
 602                 drive_reset(drive);
 603
 604                 // JRL: Should we abort here?
 605                 ide_abort_command(dev, channel);
 606             } else {
 607
 608                 atapi_identify_device(drive);
 609
 610                 channel->error_reg.val = 0;
 611                 channel->status.val = 0x58; // ready, data_req, seek_complete
 612
 613                 ide_raise_irq(dev, channel);
 614             }
 615             break;
 616         case 0xec: // Identify Device
 617             if (drive->drive_type != IDE_DISK) {
 618                 drive_reset(drive);
 619
 620                 // JRL: Should we abort here?
 621                 ide_abort_command(dev, channel);
 622             } else {
 623                 ata_identify_device(drive);
 624
 625                 channel->error_reg.val = 0;
 626                 channel->status.val = 0x58;
 627
 628                 ide_raise_irq(dev, channel);
 629             }
 630             break;
 631
 632         case 0xa0: // ATAPI Command Packet
 633             if (drive->drive_type != IDE_CDROM) {
 634                 ide_abort_command(dev, channel);
 635             }
 636
 637             drive->sector_count = 1;
 638
 639             channel->status.busy = 0;
 640             channel->status.write_fault = 0;
 641             channel->status.data_req = 1;
 642             channel->status.error = 0;
 643
 644             // reset the data buffer...
 645             drive->transfer_length = ATAPI_PACKET_SIZE;
 646             drive->transfer_index = 0;
 647
 648             break;
 649
 650         case 0x20: // Read Sectors with Retry
 651         case 0x21: // Read Sectors without Retry
 652             drive->hd_state.cur_sector_num = 1;
 653
 654             if (ata_read_sectors(dev, channel) == -1) {
 655                 PrintError("Error reading sectors\n");
 656                 return -1;
 657             }
 658             break;
 659
 660         case 0x24: // Read Sectors Extended
 661             drive->hd_state.cur_sector_num = 1;
 662
 663             if (ata_read_sectors_ext(dev, channel) == -1) {
 664                 PrintError("Error reading extended sectors\n");
 665                 return -1;
 666             }
 667             break;
 668
 669         case 0xc8: // Read DMA with retry
 670         case 0xc9: // Read DMA
 671             drive->hd_state.cur_sector_num = 1;
 672
 673             break;
 674         case 0xef: // Set Features
 675             // Prior to this the features register has been written to.
 676             // This command tells the drive to check if the new value is supported (the value is drive specific)
 677             // Common is that bit0=DMA enable
 678             // If valid the drive raises an interrupt, if not it aborts.
 679
 680             // Do some checking here...
 681
 682             channel->status.busy = 0;
 683             channel->status.write_fault = 0;
 684             channel->status.error = 0;
 685             channel->status.ready = 1;
 686             channel->status.seek_complete = 1;
 687
 688             ide_raise_irq(dev, channel);
 689             break;
 690
 691         case 0x91:  // Initialize Drive Parameters
 692         case 0x10:  // recalibrate?
 693             channel->status.error = 0;
 694             channel->status.ready = 1;
 695             channel->status.seek_complete = 1;
 696             ide_raise_irq(dev, channel);
 697             break;
 698         case 0xc6: { // Set multiple mode (IDE Block mode)
 699             // This makes the drive transfer multiple sectors before generating an interrupt
 700             uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
 701
 702             if (tmp_sect_num > MAX_MULT_SECTORS) {
 703                 ide_abort_command(dev, channel);
 704                 break;
 705             }
 706
 707             if (drive->sector_count == 0) {
 708                 drive->hd_state.mult_sector_num= 1;
 709             } else {
 710                 drive->hd_state.mult_sector_num = drive->sector_count;
 711             }
 712
 713             channel->status.ready = 1;
 714             channel->status.error = 0;
 715
 716             ide_raise_irq(dev, channel);
 717
 718             break;
 719         }
 720         case 0xc4:  // read multiple sectors
 721             drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
 722         default:
 723             PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
 724             return -1;
 725     }
 726
 727     return length;
 728 }
 729
 730
 731 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
 732     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 733     struct ide_channel * channel = get_selected_channel(ide, port);
 734     struct ide_drive * drive = get_selected_drive(channel);
 735
 736     //    PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
 737     //         port, *(uint32_t *)src, length);
 738
 739     memcpy(drive->data_buf + drive->transfer_index, src, length);
 740     drive->transfer_index += length;
 741
 742     // Transfer is complete, dispatch the command
 743     if (drive->transfer_index >= drive->transfer_length) {
 744         switch (channel->cmd_reg) {
 745             case 0x30: // Write Sectors
 746                 PrintError("Writing Data not yet implemented\n");
 747                 return -1;
 748
 749             case 0xa0: // ATAPI packet command
 750                 if (atapi_handle_packet(dev, channel) == -1) {
 751                     PrintError("Error handling ATAPI packet\n");
 752                     return -1;
 753                 }
 754                 break;
 755             default:
 756                 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
 757                 return -1;
 758         }
 759     }
 760
 761     return length;
 762 }
 763
 764
 765 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
 766     struct ide_drive * drive = get_selected_drive(channel);
 767     int data_offset = drive->transfer_index % IDE_SECTOR_SIZE;
 768
 769
 770
 771     if (drive->transfer_index >= drive->transfer_length) {
 772         PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n",
 773                    drive->transfer_length, drive->transfer_index,
 774                    drive->transfer_index + length);
 775         return -1;
 776     }
 777
 778
 779     if ((data_offset == 0) && (drive->transfer_index > 0)) {
 780         drive->current_lba++;
 781
 782         if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
 783             PrintError("Could not read next disk sector\n");
 784             return -1;
 785         }
 786     }
 787
 788     /*
 789       PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n",
 790       *(uint32_t *)(drive->data_buf + data_offset),
 791       length, data_offset);
 792     */
 793     memcpy(dst, drive->data_buf + data_offset, length);
 794
 795     drive->transfer_index += length;
 796
 797
 798     /* This is the trigger for interrupt injection.
 799      * For read single sector commands we interrupt after every sector
 800      * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
 801      * cur_sector_num is configured depending on the operation we are currently running
 802      * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
 803      */
 804     if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
 805         (drive->transfer_index == drive->transfer_length)) {
 806         if (drive->transfer_index < drive->transfer_length) {
 807             // An increment is complete, but there is still more data to be transferred...
 808             PrintDebug("Integral Complete, still transferring more sectors\n");
 809             channel->status.data_req = 1;
 810
 811             drive->irq_flags.c_d = 0;
 812         } else {
 813             PrintDebug("Final Sector Transferred\n");
 814             // This was the final read of the request
 815             channel->status.data_req = 0;
 816
 817
 818             drive->irq_flags.c_d = 1;
 819             drive->irq_flags.rel = 0;
 820         }
 821
 822         channel->status.ready = 1;
 823         drive->irq_flags.io_dir = 1;
 824         channel->status.busy = 0;
 825
 826         ide_raise_irq(dev, channel);
 827     }
 828
 829
 830     return length;
 831 }
 832
 833
 834
 835 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
 836     struct ide_drive * drive = get_selected_drive(channel);
 837     int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE;
 838     int req_offset = drive->transfer_index % drive->req_len;
 839
 840     if (drive->cd_state.atapi_cmd != 0x28) {
 841         PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
 842     }
 843
 844     if (drive->transfer_index >= drive->transfer_length) {
 845         PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
 846                    drive->transfer_length, drive->transfer_index,
 847                    drive->transfer_index + length);
 848         return -1;
 849     }
 850
 851
 852
 853     if ((data_offset == 0) && (drive->transfer_index > 0)) {
 854         if (atapi_update_data_buf(dev, channel) == -1) {
 855             PrintError("Could not update CDROM data buffer\n");
 856             return -1;
 857         }
 858     }
 859
 860     memcpy(dst, drive->data_buf + data_offset, length);
 861
 862     drive->transfer_index += length;
 863
 864
 865     // Should the req_offset be recalculated here?????
 866     if ((req_offset == 0) && (drive->transfer_index > 0)) {
 867         if (drive->transfer_index < drive->transfer_length) {
 868             // An increment is complete, but there is still more data to be transferred...
 869
 870             channel->status.data_req = 1;
 871
 872             drive->irq_flags.c_d = 0;
 873
 874             // Update the request length in the cylinder regs
 875             if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
 876                 PrintError("Could not update request length after completed increment\n");
 877                 return -1;
 878             }
 879         } else {
 880             // This was the final read of the request
 881             channel->status.data_req = 0;
 882             channel->status.ready = 1;
 883
 884             drive->irq_flags.c_d = 1;
 885             drive->irq_flags.rel = 0;
 886         }
 887
 888         drive->irq_flags.io_dir = 1;
 889         channel->status.busy = 0;
 890
 891         ide_raise_irq(dev, channel);
 892     }
 893
 894     return length;
 895 }
 896
 897
 898 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
 899     struct ide_drive * drive = get_selected_drive(channel);
 900
 901     channel->status.busy = 0;
 902     channel->status.ready = 1;
 903     channel->status.write_fault = 0;
 904     channel->status.seek_complete = 1;
 905     channel->status.corrected = 0;
 906     channel->status.error = 0;
 907
 908
 909     memcpy(dst, drive->data_buf + drive->transfer_index, length);
 910     drive->transfer_index += length;
 911
 912     if (drive->transfer_index >= drive->transfer_length) {
 913         channel->status.data_req = 0;
 914     }
 915
 916     return length;
 917 }
 918
 919
 920 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
 921     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 922     struct ide_channel * channel = get_selected_channel(ide, port);
 923     struct ide_drive * drive = get_selected_drive(channel);
 924
 925     //    PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
 926
 927     if ((channel->cmd_reg == 0xec) ||
 928         (channel->cmd_reg == 0xa1)) {
 929         return read_drive_id((uint8_t *)dst, length, dev, channel);
 930     }
 931
 932     if (drive->drive_type == IDE_CDROM) {
 933         if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
 934             PrintError("IDE: Could not read CD Data\n");
 935             return -1;
 936         }
 937     } else if (drive->drive_type == IDE_DISK) {
 938         if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
 939             PrintError("IDE: Could not read HD Data\n");
 940             return -1;
 941         }
 942     } else {
 943         memset((uint8_t *)dst, 0, length);
 944     }
 945
 946     return length;
 947 }
 948
 949 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
 950     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
 951     struct ide_channel * channel = get_selected_channel(ide, port);
 952     struct ide_drive * drive = get_selected_drive(channel);
 953
 954     if (length != 1) {
 955         PrintError("Invalid Write length on IDE port %x\n", port);
 956         return -1;
 957     }
 958
 959     PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
 960
 961     switch (port) {
 962         // reset and interrupt enable
 963         case PRI_CTRL_PORT:
 964         case SEC_CTRL_PORT: {
 965             struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
 966
 967             // only reset channel on a 0->1 reset bit transition
 968             if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
 969                 channel_reset(channel);
 970             } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
 971                 channel_reset_complete(channel);
 972             }
 973
 974             channel->ctrl_reg.val = tmp_ctrl->val;
 975             break;
 976         }
 977         case PRI_FEATURES_PORT:
 978         case SEC_FEATURES_PORT:
 979             channel->features.val = *(uint8_t *)src;
 980             break;
 981
 982         case PRI_SECT_CNT_PORT:
 983         case SEC_SECT_CNT_PORT:
 984             channel->drives[0].sector_count = *(uint8_t *)src;
 985             channel->drives[1].sector_count = *(uint8_t *)src;
 986             break;
 987
 988         case PRI_SECT_NUM_PORT:
 989         case SEC_SECT_NUM_PORT:
 990             channel->drives[0].sector_num = *(uint8_t *)src;
 991             channel->drives[1].sector_num = *(uint8_t *)src;
 992             break;
 993         case PRI_CYL_LOW_PORT:
 994         case SEC_CYL_LOW_PORT:
 995             channel->drives[0].cylinder_low = *(uint8_t *)src;
 996             channel->drives[1].cylinder_low = *(uint8_t *)src;
 997             break;
 998
 999         case PRI_CYL_HIGH_PORT:
1000         case SEC_CYL_HIGH_PORT:
1001             channel->drives[0].cylinder_high = *(uint8_t *)src;
1002             channel->drives[1].cylinder_high = *(uint8_t *)src;
1003             break;
1004
1005         case PRI_DRV_SEL_PORT:
1006         case SEC_DRV_SEL_PORT: {
1007             channel->drive_head.val = *(uint8_t *)src;
1008
1009             // make sure the reserved bits are ok..
1010             // JRL TODO: check with new ramdisk to make sure this is right...
1011             channel->drive_head.val |= 0xa0;
1012
1013             drive = get_selected_drive(channel);
1014
1015             // Selecting a non-present device is a no-no
1016             if (drive->drive_type == IDE_NONE) {
1017                 PrintDebug("Attempting to select a non-present drive\n");
1018                 channel->error_reg.abort = 1;
1019                 channel->status.error = 1;
1020             }
1021
1022             break;
1023         }
1024         default:
1025             PrintError("IDE: Write to unknown Port %x\n", port);
1026             return -1;
1027     }
1028     return length;
1029 }
1030
1031
1032 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
1033     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1034     struct ide_channel * channel = get_selected_channel(ide, port);
1035     struct ide_drive * drive = get_selected_drive(channel);
1036
1037     if (length != 1) {
1038         PrintError("Invalid Read length on IDE port %x\n", port);
1039         return -1;
1040     }
1041
1042     PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
1043
1044     if ((port == PRI_ADDR_REG_PORT) ||
1045         (port == SEC_ADDR_REG_PORT)) {
1046         // unused, return 0xff
1047         *(uint8_t *)dst = 0xff;
1048         return length;
1049     }
1050
1051
1052     // if no drive is present just return 0 + reserved bits
1053     if (drive->drive_type == IDE_NONE) {
1054         if ((port == PRI_DRV_SEL_PORT) ||
1055             (port == SEC_DRV_SEL_PORT)) {
1056             *(uint8_t *)dst = 0xa0;
1057         } else {
1058             *(uint8_t *)dst = 0;
1059         }
1060
1061         return length;
1062     }
1063
1064     switch (port) {
1065
1066         // This is really the error register.
1067         case PRI_FEATURES_PORT:
1068         case SEC_FEATURES_PORT:
1069             *(uint8_t *)dst = channel->error_reg.val;
1070             break;
1071
1072         case PRI_SECT_CNT_PORT:
1073         case SEC_SECT_CNT_PORT:
1074             *(uint8_t *)dst = drive->sector_count;
1075             break;
1076
1077         case PRI_SECT_NUM_PORT:
1078         case SEC_SECT_NUM_PORT:
1079             *(uint8_t *)dst = drive->sector_num;
1080             break;
1081
1082         case PRI_CYL_LOW_PORT:
1083         case SEC_CYL_LOW_PORT:
1084             *(uint8_t *)dst = drive->cylinder_low;
1085             break;
1086
1087
1088         case PRI_CYL_HIGH_PORT:
1089         case SEC_CYL_HIGH_PORT:
1090             *(uint8_t *)dst = drive->cylinder_high;
1091             break;
1092
1093         case PRI_DRV_SEL_PORT:
1094         case SEC_DRV_SEL_PORT:  // hard disk drive and head register 0x1f6
1095             *(uint8_t *)dst = channel->drive_head.val;
1096             break;
1097
1098         case PRI_CTRL_PORT:
1099         case SEC_CTRL_PORT:
1100         case PRI_CMD_PORT:
1101         case SEC_CMD_PORT:
1102             // Something about lowering interrupts here....
1103             *(uint8_t *)dst = channel->status.val;
1104             break;
1105
1106         default:
1107             PrintError("Invalid Port: %x\n", port);
1108             return -1;
1109     }
1110
1111     PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1112
1113     return length;
1114 }
1115
1116
1117
1118 static void init_drive(struct ide_drive * drive) {
1119
1120     drive->sector_count = 0x01;
1121     drive->sector_num = 0x01;
1122     drive->cylinder = 0x0000;
1123
1124     drive->drive_type = IDE_NONE;
1125
1126     memset(drive->model, 0, sizeof(drive->model));
1127
1128     drive->transfer_index = 0;
1129     drive->transfer_length = 0;
1130     memset(drive->data_buf, 0, sizeof(drive->data_buf));
1131
1132
1133     drive->private_data = NULL;
1134     drive->cd_ops = NULL;
1135 }
1136
1137 static void init_channel(struct ide_channel * channel) {
1138     int i = 0;
1139
1140     channel->error_reg.val = 0x01;
1141     channel->drive_head.val = 0x00;
1142     channel->status.val = 0x00;
1143     channel->cmd_reg = 0x00;
1144     channel->ctrl_reg.val = 0x08;
1145
1146
1147     channel->dma_cmd.val = 0;
1148     channel->dma_status.val = 0;
1149     channel->dma_prd_addr = 0;
1150     channel->dma_tbl_index = 0;
1151
1152     for (i = 0; i < 2; i++) {
1153         init_drive(&(channel->drives[i]));
1154     }
1155
1156 }
1157
1158
1159 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
1160     PrintDebug("PCI Config Update\n");
1161     PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
1162
1163     return 0;
1164 }
1165
1166 static int init_ide_state(struct vm_device * dev) {
1167     struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1168     int i, j;
1169
1170
1171     /*
1172        Check if the PIIX 3 actually represents both IDE channels in a single PCI entry */
1173
1174     for (i = 0; i < 1; i++) {
1175         init_channel(&(ide->channels[i]));
1176
1177         // JRL: this is a terrible hack...
1178         ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1179
1180
1181         if (ide->pci) {
1182             struct v3_pci_bar bars[6];
1183             struct pci_device * pci_dev = NULL;
1184
1185             for (j = 0; j < 6; j++) {
1186                 bars[j].type = PCI_BAR_NONE;
1187             }
1188
1189
1190             bars[4].type = PCI_BAR_IO;
1191             bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8);
1192             bars[4].num_ports = 8;
1193
1194             if (i == 0) {
1195                 bars[4].io_read = read_pri_dma_port;
1196                 bars[4].io_write = write_pri_dma_port;
1197             } else {
1198                 bars[4].io_read = read_sec_dma_port;
1199                 bars[4].io_write = write_sec_dma_port;
1200             }
1201
1202             pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
1203                                              pci_config_update, NULL, NULL, dev);
1204
1205             if (pci_dev == NULL) {
1206                 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1207                 return -1;
1208             }
1209
1210             ide->channels[i].pci_dev = pci_dev;
1211
1212             /* This is for CMD646 devices
1213                pci_dev->config_header.vendor_id = 0x1095;
1214                pci_dev->config_header.device_id = 0x0646;
1215                pci_dev->config_header.revision = 0x8f07;
1216             */
1217             pci_dev->config_header.vendor_id = 0x8086;
1218             pci_dev->config_header.device_id = 0x7010;
1219             pci_dev->config_header.revision = 0x8000;
1220
1221             pci_dev->config_header.subclass = 0x01;
1222             pci_dev->config_header.class = 0x01;
1223
1224
1225             pci_dev->config_header.command = 0;
1226             pci_dev->config_header.status = 0x0280;
1227
1228             //      pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i;
1229             //      pci_dev->config_header.intr_pin = 1;
1230         }
1231
1232
1233     }
1234
1235     return 0;
1236 }
1237
1238
1239
1240 static int init_ide(struct vm_device * dev) {
1241     //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1242
1243     PrintDebug("IDE: Initializing IDE\n");
1244
1245     if (init_ide_state(dev) == -1) {
1246         PrintError("Failed to initialize IDE state\n");
1247         return -1;
1248     }
1249
1250
1251     v3_dev_hook_io(dev, PRI_DATA_PORT,
1252                    &ide_read_data_port, &write_data_port);
1253     v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1254                    &read_port_std, &write_port_std);
1255     v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1256                    &read_port_std, &write_port_std);
1257     v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1258                    &read_port_std, &write_port_std);
1259     v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1260                    &read_port_std, &write_port_std);
1261     v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1262                    &read_port_std, &write_port_std);
1263     v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1264                    &read_port_std, &write_port_std);
1265     v3_dev_hook_io(dev, PRI_CMD_PORT,
1266                    &read_port_std, &write_cmd_port);
1267
1268     v3_dev_hook_io(dev, SEC_DATA_PORT,
1269                    &ide_read_data_port, &write_data_port);
1270     v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1271                    &read_port_std, &write_port_std);
1272     v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1273                    &read_port_std, &write_port_std);
1274     v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1275                    &read_port_std, &write_port_std);
1276     v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1277                    &read_port_std, &write_port_std);
1278     v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1279                    &read_port_std, &write_port_std);
1280     v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1281                    &read_port_std, &write_port_std);
1282     v3_dev_hook_io(dev, SEC_CMD_PORT,
1283                    &read_port_std, &write_cmd_port);
1284
1285
1286     v3_dev_hook_io(dev, PRI_CTRL_PORT,
1287                    &read_port_std, &write_port_std);
1288
1289     v3_dev_hook_io(dev, SEC_CTRL_PORT,
1290                    &read_port_std, &write_port_std);
1291
1292
1293     v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1294                    &read_port_std, &write_port_std);
1295
1296     v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1297                    &read_port_std, &write_port_std);
1298
1299     return 0;
1300 }
1301
1302
1303 static int deinit_ide(struct vm_device * dev) {
1304     // unhook io ports....
1305     // deregister from PCI?
1306     return 0;
1307 }
1308
1309
1310 static struct vm_device_ops dev_ops = {
1311     .init = init_ide,
1312     .deinit = deinit_ide,
1313     .reset = NULL,
1314     .start = NULL,
1315     .stop = NULL,
1316 };
1317
1318
1319 struct vm_device *  v3_create_ide(struct vm_device * pci, struct vm_device * southbridge) {
1320     struct ide_internal * ide  = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1321     struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1322
1323     ide->pci = pci;
1324     ide->southbridge = southbridge;
1325
1326     PrintDebug("IDE: Creating IDE bus x 2\n");
1327
1328     return device;
1329 }
1330
1331
1332
1333
1334
1335 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1336                           uint_t bus_num,
1337                           uint_t drive_num,
1338                           char * dev_name,
1339                           struct v3_ide_cd_ops * ops,
1340                           void * private_data) {
1341
1342     struct ide_internal * ide  = (struct ide_internal *)(ide_dev->private_data);
1343     struct ide_channel * channel = NULL;
1344     struct ide_drive * drive = NULL;
1345
1346     V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1347     V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1348
1349     channel = &(ide->channels[bus_num]);
1350     drive = &(channel->drives[drive_num]);
1351
1352     if (drive->drive_type != IDE_NONE) {
1353         PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1354         return -1;
1355     }
1356
1357     strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1358
1359     while (strlen((char *)(drive->model)) < 40) {
1360         strcat((char*)(drive->model), " ");
1361     }
1362
1363
1364     drive->drive_type = IDE_CDROM;
1365
1366     drive->cd_ops = ops;
1367
1368     drive->private_data = private_data;
1369
1370     return 0;
1371 }
1372
1373
1374 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1375                              uint_t bus_num,
1376                              uint_t drive_num,
1377                              char * dev_name,
1378                              struct v3_ide_hd_ops * ops,
1379                              void * private_data) {
1380
1381     struct ide_internal * ide  = (struct ide_internal *)(ide_dev->private_data);
1382     struct ide_channel * channel = NULL;
1383     struct ide_drive * drive = NULL;
1384
1385     V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1386     V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1387
1388     channel = &(ide->channels[bus_num]);
1389     drive = &(channel->drives[drive_num]);
1390
1391     if (drive->drive_type != IDE_NONE) {
1392         PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1393         return -1;
1394     }
1395
1396     strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1397
1398     drive->drive_type = IDE_DISK;
1399
1400     drive->hd_state.accessed = 0;
1401     drive->hd_state.mult_sector_num = 1;
1402
1403     drive->hd_ops = ops;
1404
1405     drive->private_data = private_data;
1406
1407     return 0;
1408 }
1409
1410
1411