1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
7 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
9 static const uint_t MASTER_PORT1 = 0x20;
10 static const uint_t MASTER_PORT2 = 0x21;
11 static const uint_t SLAVE_PORT1 = 0xA0;
12 static const uint_t SLAVE_PORT2 = 0xA1;
14 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
15 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
18 uint_t ic4 : 1; // ICW4 has to be read
19 uint_t sngl : 1; // single (only one PIC)
20 uint_t adi : 1; // call address interval
21 uint_t ltim : 1; // level interrupt mode
33 // Each bit that is set indicates that the IR input has a slave
45 // The ID is the Slave device ID
52 uint_t uPM : 1; // 1=x86
53 uint_t AEOI : 1; // Automatic End of Interrupt
54 uint_t M_S : 1; // only if buffered 1=master,0=slave
55 uint_t BUF : 1; // buffered mode
56 uint_t SFNM : 1; // special fully nexted mode
74 uint_t cw_code : 2; // should be 00
84 uint_t cw_code : 2; // should be 01
119 pic_state_t master_state;
120 pic_state_t slave_state;
125 static int pic_raise_intr(void * private_data, int irq, int error_code) {
126 struct pic_internal * state = (struct pic_internal*)private_data;
133 state->master_irr |= 0x01 << irq;
134 } else if ((irq > 7) && (irq < 16)) {
135 state->slave_irr |= 0x01 << (irq - 7);
143 static int pic_intr_pending(void * private_data) {
144 struct pic_internal * state = (struct pic_internal*)private_data;
146 if ((state->master_irr & ~(state->master_imr)) ||
147 (state->slave_irr & ~(state->slave_imr))) {
154 static int pic_get_intr_number(void * private_data) {
155 struct pic_internal * state = (struct pic_internal*)private_data;
158 for (i = 0; i < 16; i++) {
160 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
161 state->master_isr |= (0x1 << i);
162 return i + state->master_icw2;
165 if (((state->slave_irr & ~(state->slave_imr)) >> i) == 0x01) {
166 state->slave_isr |= (0x1 << i);
167 return i + state->slave_icw2;
176 static int pic_begin_irq(void * private_data, int irq) {
182 static int pic_end_irq(void * private_data, int irq) {
188 static struct intr_ctrl_ops intr_ops = {
189 .intr_pending = pic_intr_pending,
190 .get_intr_number = pic_get_intr_number,
191 .raise_intr = pic_raise_intr,
192 .begin_irq = pic_begin_irq,
201 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
202 struct pic_internal * state = (struct pic_internal*)dev->private_data;
207 if ((state->master_ocw3 & 0x03) == 0x02) {
208 *(char *)dst = state->master_irr;
209 } else if ((state->master_ocw3 & 0x03) == 0x03) {
210 *(char *)dst = state->master_isr;
218 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
219 struct pic_internal * state = (struct pic_internal*)dev->private_data;
224 *(char *)dst = state->master_imr;
230 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
231 struct pic_internal * state = (struct pic_internal*)dev->private_data;
236 if ((state->slave_ocw3 & 0x03) == 0x02) {
237 *(char*)dst = state->slave_irr;
238 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
239 *(char *)dst = state->slave_isr;
247 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
248 struct pic_internal * state = (struct pic_internal*)dev->private_data;
253 *(char *)dst = state->slave_imr;
259 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
260 struct pic_internal * state = (struct pic_internal*)dev->private_data;
261 char cw = *(char *)src;
267 if (state->master_state == ICW1) {
268 state->master_icw1 = cw;
269 state->master_state = ICW2;
270 } else if (state->master_state == READY) {
272 // handle the EOI here
273 struct ocw2 * cw2 = (struct ocw2*)&cw;
275 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
277 state->master_isr &= ~(0x01 << cw2->level);
278 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
285 state->master_ocw2 = cw;
286 } else if (IS_OCW3(cw)) {
287 state->master_ocw3 = cw;
298 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
299 struct pic_internal * state = (struct pic_internal*)dev->private_data;
300 char cw = *(char *)src;
306 if (state->master_state == ICW2) {
307 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
309 state->master_icw2 = cw;
311 if (cw1->sngl == 0) {
312 state->master_state = ICW3;
313 } else if (cw1->ic4 == 1) {
314 state->master_state = ICW4;
316 state->master_state = READY;
319 } else if (state->master_state == ICW3) {
320 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
322 state->master_icw3 = cw;
325 state->master_state = ICW4;
327 state->master_state = READY;
330 } else if (state->master_state == ICW4) {
331 state->master_icw4 = cw;
332 state->master_state = READY;
333 } else if (state->master_state == READY) {
334 state->master_imr = cw;
342 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
343 struct pic_internal * state = (struct pic_internal*)dev->private_data;
344 char cw = *(char *)src;
350 if (state->slave_state == ICW1) {
351 state->slave_icw1 = cw;
352 state->slave_state = ICW2;
353 } else if (state->slave_state == READY) {
355 // handle the EOI here
356 struct ocw2 * cw2 = (struct ocw2 *)&cw;
358 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
360 state->slave_isr &= ~(0x01 << cw2->level);
361 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
367 state->slave_ocw2 = cw;
368 } else if (IS_OCW3(cw)) {
369 // Basically sets the IRR/ISR read flag
370 state->slave_ocw3 = cw;
381 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
382 struct pic_internal * state = (struct pic_internal*)dev->private_data;
383 char cw = *(char *)src;
389 if (state->slave_state == ICW2) {
390 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
392 state->slave_icw2 = cw;
394 if (cw1->sngl == 0) {
395 state->slave_state = ICW3;
396 } else if (cw1->ic4 == 1) {
397 state->slave_state = ICW4;
399 state->slave_state = READY;
402 } else if (state->slave_state == ICW3) {
403 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
405 state->slave_icw3 = cw;
408 state->slave_state = ICW4;
410 state->slave_state = READY;
413 } else if (state->slave_state == ICW4) {
414 state->slave_icw4 = cw;
415 state->slave_state = READY;
416 } else if (state->slave_state == READY) {
417 state->slave_imr = cw;
432 int pic_init(struct vm_device * dev) {
433 struct pic_internal * state = (struct pic_internal*)dev->private_data;
435 set_intr_controller(dev->vm, &intr_ops, state);
437 state->master_irr = 0;
438 state->master_isr = 0;
439 state->master_icw1 = 0;
440 state->master_icw2 = 0;
441 state->master_icw3 = 0;
442 state->master_icw4 = 0;
443 state->master_imr = 0;
444 state->master_ocw2 = 0;
445 state->master_ocw3 = 0x02;
446 state->master_state = ICW1;
449 state->slave_irr = 0;
450 state->slave_isr = 0;
451 state->slave_icw1 = 0;
452 state->slave_icw2 = 0;
453 state->slave_icw3 = 0;
454 state->slave_icw4 = 0;
455 state->slave_imr = 0;
456 state->slave_ocw2 = 0;
457 state->slave_ocw3 = 0x02;
458 state->slave_state = ICW1;
461 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
462 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
463 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
464 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
470 int pic_deinit(struct vm_device * dev) {
471 dev_unhook_io(dev, MASTER_PORT1);
472 dev_unhook_io(dev, MASTER_PORT2);
473 dev_unhook_io(dev, SLAVE_PORT1);
474 dev_unhook_io(dev, SLAVE_PORT2);
485 static struct vm_device_ops dev_ops = {
487 .deinit = pic_deinit,
494 struct vm_device * create_pic() {
495 struct pic_internal * state = NULL;
496 VMMMalloc(struct pic_internal *, state, sizeof(struct pic_internal));
498 struct vm_device *device = create_device("8259A", &dev_ops, state);