2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm_types.h>
22 /* .... Giant fucking switch tables */
137 static int get_addr_width(struct guest_info * info, struct x86_instr * instr) {
139 switch (v3_get_vm_cpu_mode(info)) {
141 return (instr->prefixes.addr_size) ? 4 : 2;
147 if (info->segments.cs.db) {
148 return (instr->prefixes.addr_size) ? 2 : 4;
150 return (instr->prefixes.addr_size) ? 4 : 2;
153 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
158 static int get_operand_width(struct guest_info * info, struct x86_instr * instr,
258 switch (v3_get_vm_cpu_mode(info)) {
260 return (instr->prefixes.op_size) ? 4 : 2;
262 if (instr->prefixes.rex_op_size) {
270 if (info->segments.cs.db) {
272 return (instr->prefixes.op_size) ? 2 : 4;
274 return (instr->prefixes.op_size) ? 4 : 2;
277 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
282 switch (v3_get_vm_cpu_mode(info)) {
284 PrintError("Invalid instruction given operating mode (%d)\n", form);
293 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
299 switch (v3_get_vm_cpu_mode(info)) {
309 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
317 switch (v3_get_vm_cpu_mode(info)) {
327 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
334 PrintError("Unsupported instruction form %d\n", form);
344 typedef enum {INVALID_ADDR_TYPE, REG, DISP0, DISP8, DISP16, DISP32} modrm_mode_t;
345 typedef enum {INVALID_REG_SIZE, REG64, REG32, REG16, REG8} reg_size_t;
352 } __attribute__((packed));
359 } __attribute__((packed));
366 static inline int decode_gpr(struct guest_info * core,
368 struct x86_operand * reg) {
370 struct v3_gprs * gprs = &(core->vm_regs);
374 reg->operand = (addr_t)&(gprs->rax);
377 reg->operand = (addr_t)&(gprs->rcx);
380 reg->operand = (addr_t)&(gprs->rdx);
383 reg->operand = (addr_t)&(gprs->rbx);
386 if (reg->size == 1) {
387 reg->operand = (addr_t)&(gprs->rax) + 1;
389 reg->operand = (addr_t)&(gprs->rsp);
393 if (reg->size == 1) {
394 reg->operand = (addr_t)&(gprs->rcx) + 1;
396 reg->operand = (addr_t)&(gprs->rbp);
400 if (reg->size == 1) {
401 reg->operand = (addr_t)&(gprs->rdx) + 1;
403 reg->operand = (addr_t)&(gprs->rsi);
407 if (reg->size == 1) {
408 reg->operand = (addr_t)&(gprs->rbx) + 1;
410 reg->operand = (addr_t)&(gprs->rdi);
414 reg->operand = (addr_t)&(gprs->r8);
417 reg->operand = (addr_t)&(gprs->r9);
420 reg->operand = (addr_t)&(gprs->r10);
423 reg->operand = (addr_t)&(gprs->r11);
426 reg->operand = (addr_t)&(gprs->r12);
429 reg->operand = (addr_t)&(gprs->r13);
432 reg->operand = (addr_t)&(gprs->r14);
435 reg->operand = (addr_t)&(gprs->r15);
438 PrintError("Invalid Reg Code (%d)\n", reg_code);
449 static inline int decode_cr(struct guest_info * core,
451 struct x86_operand * reg) {
453 struct v3_ctrl_regs * crs = &(core->ctrl_regs);
455 // PrintDebug("\t Ctrl regs %d\n", reg_code);
459 reg->operand = (addr_t)&(crs->cr0);
462 reg->operand = (addr_t)&(crs->cr2);
465 reg->operand = (addr_t)&(crs->cr3);
468 reg->operand = (addr_t)&(crs->cr4);
472 PrintError("Invalid Reg Code (%d)\n", reg_code);
479 // This converts the displacement into the appropriate masked value
481 QUESTION: Are the register Values signed ?????
483 #define MASK_DISPLACEMENT(reg, mode) ({ \
485 if (mode == DISP0) { \
487 } else if (mode == DISP8) { \
488 val = (sint8_t)(reg & 0xff); \
489 } else if (mode == DISP16) { \
490 val = (sint16_t)(reg & 0xffff); \
491 } else if (mode == DISP32) { \
492 val = (sint32_t)(reg & 0xffffffff); \
494 PrintError("Error invalid displacement size (%d)\n", mode); \
501 #define ADDR_MASK(val, length) ({ \
502 ullong_t mask = 0x0LL; \
505 mask = 0x0000000000000ffLL; \
508 mask = 0x00000000000fffffLL; \
511 mask = 0x00000000ffffffffLL; \
514 mask = 0xffffffffffffffffLL; \
522 static int decode_rm_operand16(struct guest_info * core,
523 uint8_t * modrm_instr,
524 struct x86_instr * instr,
525 struct x86_operand * operand,
526 uint8_t * reg_code) {
528 struct v3_gprs * gprs = &(core->vm_regs);
529 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
530 addr_t base_addr = 0;
531 modrm_mode_t mod_mode = 0;
532 uint8_t * instr_cursor = modrm_instr;
534 // PrintDebug("ModRM mod=%d\n", modrm->mod);
536 *reg_code = modrm->reg;
540 if (modrm->mod == 3) {
541 //PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
542 operand->type = REG_OPERAND;
544 decode_gpr(core, modrm->rm, operand);
547 struct v3_segment * seg = NULL;
549 operand->type = MEM_OPERAND;
551 if (modrm->mod == 0) {
553 } else if (modrm->mod == 1) {
555 } else if (modrm->mod == 2) {
558 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
559 v3_print_instr(instr);
565 base_addr = gprs->rbx + ADDR_MASK(gprs->rsi, 2);
568 base_addr = gprs->rbx + ADDR_MASK(gprs->rdi, 2);
571 base_addr = gprs->rbp + ADDR_MASK(gprs->rsi, 2);
574 base_addr = gprs->rbp + ADDR_MASK(gprs->rdi, 2);
577 base_addr = ADDR_MASK(gprs->rsi, 2);
580 base_addr = ADDR_MASK(gprs->rdi, 2);
583 if (modrm->mod == 0) {
587 base_addr = ADDR_MASK(gprs->rbp, 2);
591 base_addr = ADDR_MASK(gprs->rbx, 2);
597 if (mod_mode == DISP8) {
598 base_addr += *(sint8_t *)instr_cursor;
600 } else if (mod_mode == DISP16) {
601 base_addr += *(sint16_t *)instr_cursor;
606 // get appropriate segment
607 if (instr->prefixes.cs_override) {
608 seg = &(core->segments.cs);
609 } else if (instr->prefixes.es_override) {
610 seg = &(core->segments.es);
611 } else if (instr->prefixes.ss_override) {
612 seg = &(core->segments.ss);
613 } else if (instr->prefixes.fs_override) {
614 seg = &(core->segments.fs);
615 } else if (instr->prefixes.gs_override) {
616 seg = &(core->segments.gs);
618 seg = &(core->segments.ds);
621 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
622 get_addr_width(core, instr));
626 return (instr_cursor - modrm_instr);
630 // returns num_bytes parsed
631 static int decode_rm_operand32(struct guest_info * core,
632 uint8_t * modrm_instr,
633 struct x86_instr * instr,
634 struct x86_operand * operand,
635 uint8_t * reg_code) {
637 struct v3_gprs * gprs = &(core->vm_regs);
638 uint8_t * instr_cursor = modrm_instr;
639 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
640 addr_t base_addr = 0;
641 modrm_mode_t mod_mode = 0;
642 uint_t has_sib_byte = 0;
645 *reg_code = modrm->reg;
649 if (modrm->mod == 3) {
650 operand->type = REG_OPERAND;
651 // PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
653 decode_gpr(core, modrm->rm, operand);
656 struct v3_segment * seg = NULL;
658 operand->type = MEM_OPERAND;
660 if (modrm->mod == 0) {
662 } else if (modrm->mod == 1) {
664 } else if (modrm->mod == 2) {
667 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
668 v3_print_instr(instr);
674 base_addr = gprs->rax;
677 base_addr = gprs->rcx;
680 base_addr = gprs->rdx;
683 base_addr = gprs->rbx;
689 if (modrm->mod == 0) {
693 base_addr = gprs->rbp;
697 base_addr = gprs->rsi;
700 base_addr = gprs->rdi;
706 struct sib_byte * sib = (struct sib_byte *)(instr_cursor);
707 int scale = 0x1 << sib->scale;
711 switch (sib->index) {
713 base_addr = gprs->rax;
716 base_addr = gprs->rcx;
719 base_addr = gprs->rdx;
722 base_addr = gprs->rbx;
728 base_addr = gprs->rbp;
731 base_addr = gprs->rsi;
734 base_addr = gprs->rdi;
743 base_addr += MASK_DISPLACEMENT(gprs->rax, mod_mode);
746 base_addr += MASK_DISPLACEMENT(gprs->rcx, mod_mode);
749 base_addr += MASK_DISPLACEMENT(gprs->rdx, mod_mode);
752 base_addr += MASK_DISPLACEMENT(gprs->rbx, mod_mode);
755 base_addr += MASK_DISPLACEMENT(gprs->rsp, mod_mode);
758 if (modrm->mod != 0) {
759 base_addr += MASK_DISPLACEMENT(gprs->rbp, mod_mode);
763 base_addr += MASK_DISPLACEMENT(gprs->rsi, mod_mode);
766 base_addr += MASK_DISPLACEMENT(gprs->rdi, mod_mode);
773 if (mod_mode == DISP8) {
774 base_addr += *(sint8_t *)instr_cursor;
776 } else if (mod_mode == DISP32) {
777 base_addr += *(sint32_t *)instr_cursor;
781 // get appropriate segment
782 if (instr->prefixes.cs_override) {
783 seg = &(core->segments.cs);
784 } else if (instr->prefixes.es_override) {
785 seg = &(core->segments.es);
786 } else if (instr->prefixes.ss_override) {
787 seg = &(core->segments.ss);
788 } else if (instr->prefixes.fs_override) {
789 seg = &(core->segments.fs);
790 } else if (instr->prefixes.gs_override) {
791 seg = &(core->segments.gs);
793 seg = &(core->segments.ds);
796 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
797 get_addr_width(core, instr));
801 return (instr_cursor - modrm_instr);
805 int decode_rm_operand64(struct guest_info * core, uint8_t * modrm_instr,
806 struct x86_instr * instr, struct x86_operand * operand,
807 uint8_t * reg_code) {
809 struct v3_gprs * gprs = &(core->vm_regs);
810 uint8_t * instr_cursor = modrm_instr;
811 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
812 addr_t base_addr = 0;
813 modrm_mode_t mod_mode = 0;
814 uint_t has_sib_byte = 0;
819 *reg_code = modrm->reg;
820 *reg_code |= (instr->prefixes.rex_reg << 3);
822 if (modrm->mod == 3) {
823 uint8_t rm_val = modrm->rm;
825 rm_val |= (instr->prefixes.rex_rm << 3);
827 operand->type = REG_OPERAND;
828 // PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
830 decode_gpr(core, rm_val, operand);
832 struct v3_segment * seg = NULL;
833 uint8_t rm_val = modrm->rm;
835 operand->type = MEM_OPERAND;
838 if (modrm->mod == 0) {
840 } else if (modrm->mod == 1) {
842 } else if (modrm->mod == 2) {
845 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
846 v3_print_instr(instr);
853 rm_val |= (instr->prefixes.rex_rm << 3);
857 base_addr = gprs->rax;
860 base_addr = gprs->rcx;
863 base_addr = gprs->rdx;
866 base_addr = gprs->rbx;
869 if (modrm->mod == 0) {
873 base_addr = gprs->rbp;
877 base_addr = gprs->rsi;
880 base_addr = gprs->rdi;
883 base_addr = gprs->r8;
886 base_addr = gprs->r9;
889 base_addr = gprs->r10;
892 base_addr = gprs->r11;
895 base_addr = gprs->r12;
898 base_addr = gprs->r13;
901 base_addr = gprs->r14;
904 base_addr = gprs->r15;
913 struct sib_byte * sib = (struct sib_byte *)(instr_cursor);
914 int scale = 0x1 << sib->scale;
915 uint8_t index_val = sib->index;
916 uint8_t base_val = sib->base;
918 index_val |= (instr->prefixes.rex_sib_idx << 3);
919 base_val |= (instr->prefixes.rex_rm << 3);
925 base_addr = gprs->rax;
928 base_addr = gprs->rcx;
931 base_addr = gprs->rdx;
934 base_addr = gprs->rbx;
940 base_addr = gprs->rbp;
943 base_addr = gprs->rsi;
946 base_addr = gprs->rdi;
949 base_addr = gprs->r8;
952 base_addr = gprs->r9;
955 base_addr = gprs->r10;
958 base_addr = gprs->r11;
961 base_addr = gprs->r12;
964 base_addr = gprs->r13;
967 base_addr = gprs->r14;
970 base_addr = gprs->r15;
979 base_addr += MASK_DISPLACEMENT(gprs->rax, mod_mode);
982 base_addr += MASK_DISPLACEMENT(gprs->rcx, mod_mode);
985 base_addr += MASK_DISPLACEMENT(gprs->rdx, mod_mode);
988 base_addr += MASK_DISPLACEMENT(gprs->rbx, mod_mode);
991 base_addr += MASK_DISPLACEMENT(gprs->rsp, mod_mode);
994 if (modrm->mod != 0) {
995 base_addr += MASK_DISPLACEMENT(gprs->rbp, mod_mode);
999 base_addr += MASK_DISPLACEMENT(gprs->rsi, mod_mode);
1002 base_addr += MASK_DISPLACEMENT(gprs->rdi, mod_mode);
1005 base_addr += MASK_DISPLACEMENT(gprs->r8, mod_mode);
1008 base_addr += MASK_DISPLACEMENT(gprs->r9, mod_mode);
1011 base_addr += MASK_DISPLACEMENT(gprs->r10, mod_mode);
1014 base_addr += MASK_DISPLACEMENT(gprs->r11, mod_mode);
1017 base_addr += MASK_DISPLACEMENT(gprs->r12, mod_mode);
1020 base_addr += MASK_DISPLACEMENT(gprs->r13, mod_mode);
1023 base_addr += MASK_DISPLACEMENT(gprs->r14, mod_mode);
1026 base_addr += MASK_DISPLACEMENT(gprs->r15, mod_mode);
1033 if (mod_mode == DISP8) {
1034 base_addr += *(sint8_t *)instr_cursor;
1036 } else if (mod_mode == DISP32) {
1037 base_addr += *(sint32_t *)instr_cursor;
1043 Segments should be ignored
1044 // get appropriate segment
1045 if (instr->prefixes.cs_override) {
1046 seg = &(core->segments.cs);
1047 } else if (instr->prefixes.es_override) {
1048 seg = &(core->segments.es);
1049 } else if (instr->prefixes.ss_override) {
1050 seg = &(core->segments.ss);
1051 } else if (instr->prefixes.fs_override) {
1052 seg = &(core->segments.fs);
1053 } else if (instr->prefixes.gs_override) {
1054 seg = &(core->segments.gs);
1056 seg = &(core->segments.ds);
1060 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
1061 get_addr_width(core, instr));
1065 return (instr_cursor - modrm_instr);
1071 static int decode_rm_operand(struct guest_info * core,
1072 uint8_t * instr_ptr, // input
1074 struct x86_instr * instr,
1075 struct x86_operand * operand,
1076 uint8_t * reg_code) {
1078 v3_cpu_mode_t mode = v3_get_vm_cpu_mode(core);
1080 operand->size = get_operand_width(core, instr, form);
1084 return decode_rm_operand16(core, instr_ptr, instr, operand, reg_code);
1086 if (instr->prefixes.rex_op_size) {
1087 return decode_rm_operand64(core, instr_ptr, instr, operand, reg_code);
1091 case LONG_32_COMPAT:
1092 return decode_rm_operand32(core, instr_ptr, instr, operand, reg_code);
1094 PrintError("Invalid CPU_MODE (%d)\n", mode);
1101 static inline op_form_t op_code_to_form_0f(uint8_t * instr, int * length) {
1106 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[2]);
1108 switch (modrm->reg) {
1116 return INVALID_INSTR;
1177 return INVALID_INSTR;
1182 static op_form_t op_code_to_form(uint8_t * instr, int * length) {
1206 return op_code_to_form_0f(instr, length);
1246 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1248 switch (modrm->reg) {
1262 return INVALID_INSTR;
1266 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1268 switch (modrm->reg) {
1282 return INVALID_INSTR;
1286 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1288 switch (modrm->reg) {
1290 return ADD_IMM2SX_8;
1294 return ADC_IMM2SX_8;
1296 return AND_IMM2SX_8;
1298 return SUB_IMM2SX_8;
1300 return XOR_IMM2SX_8;
1302 return INVALID_INSTR;
1331 return MOV_MEM2AL_8;
1335 return MOV_AL2MEM_8;
1359 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1361 switch (modrm->reg) {
1367 return INVALID_INSTR;
1371 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1373 switch (modrm->reg) {
1379 return INVALID_INSTR;
1385 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1387 switch (modrm->reg) {
1393 return INVALID_INSTR;
1398 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1400 switch (modrm->reg) {
1406 return INVALID_INSTR;
1411 return INVALID_INSTR;
1417 static char * op_form_to_str(op_form_t form) {
1420 case LMSW: return "LMSW";
1421 case SMSW: return "SMSW";
1422 case CLTS: return "CLTS";
1423 case INVLPG: return "INVLPG";
1424 case MOV_CR2: return "MOV_CR2";
1425 case MOV_2CR: return "MOV_2CR";
1426 case MOV_DR2: return "MOV_DR2";
1427 case MOV_2DR: return "MOV_2DR";
1428 case MOV_SR2: return "MOV_SR2";
1429 case MOV_2SR: return "MOV_2SR";
1430 case MOV_MEM2_8: return "MOV_MEM2_8";
1431 case MOV_MEM2: return "MOV_MEM2";
1432 case MOV_2MEM_8: return "MOV_2MEM_8";
1433 case MOV_2MEM: return "MOV_2MEM";
1434 case MOV_MEM2AL_8: return "MOV_MEM2AL_8";
1435 case MOV_MEM2AX: return "MOV_MEM2AX";
1436 case MOV_AL2MEM_8: return "MOV_AL2MEM_8";
1437 case MOV_AX2MEM: return "MOV_AX2MEM";
1438 case MOV_IMM2_8: return "MOV_IMM2_8";
1439 case MOV_IMM2: return "MOV_IMM2";
1440 case MOVS_8: return "MOVS_8";
1441 case MOVS: return "MOVS";
1442 case MOVSX_8: return "MOVSX_8";
1443 case MOVSX: return "MOVSX";
1444 case MOVZX_8: return "MOVZX_8";
1445 case MOVZX: return "MOVZX";
1446 case HLT: return "HLT";
1447 case PUSHF: return "PUSHF";
1448 case POPF: return "POPF";
1449 case ADC_2MEM_8: return "ADC_2MEM_8";
1450 case ADC_2MEM: return "ADC_2MEM";
1451 case ADC_MEM2_8: return "ADC_MEM2_8";
1452 case ADC_MEM2: return "ADC_MEM2";
1453 case ADC_IMM2_8: return "ADC_IMM2_8";
1454 case ADC_IMM2: return "ADC_IMM2";
1455 case ADC_IMM2SX_8: return "ADC_IMM2SX_8";
1456 case ADD_IMM2_8: return "ADD_IMM2_8";
1457 case ADD_IMM2: return "ADD_IMM2";
1458 case ADD_IMM2SX_8: return "ADD_IMM2SX_8";
1459 case ADD_2MEM_8: return "ADD_2MEM_8";
1460 case ADD_2MEM: return "ADD_2MEM";
1461 case ADD_MEM2_8: return "ADD_MEM2_8";
1462 case ADD_MEM2: return "ADD_MEM2";
1463 case AND_MEM2_8: return "AND_MEM2_8";
1464 case AND_MEM2: return "AND_MEM2";
1465 case AND_2MEM_8: return "AND_2MEM_8";
1466 case AND_2MEM: return "AND_2MEM";
1467 case AND_IMM2_8: return "AND_IMM2_8";
1468 case AND_IMM2: return "AND_IMM2";
1469 case AND_IMM2SX_8: return "AND_IMM2SX_8";
1470 case OR_2MEM_8: return "OR_2MEM_8";
1471 case OR_2MEM: return "OR_2MEM";
1472 case OR_MEM2_8: return "OR_MEM2_8";
1473 case OR_MEM2: return "OR_MEM2";
1474 case OR_IMM2_8: return "OR_IMM2_8";
1475 case OR_IMM2: return "OR_IMM2";
1476 case OR_IMM2SX_8: return "OR_IMM2SX_8";
1477 case SUB_2MEM_8: return "SUB_2MEM_8";
1478 case SUB_2MEM: return "SUB_2MEM";
1479 case SUB_MEM2_8: return "SUB_MEM2_8";
1480 case SUB_MEM2: return "SUB_MEM2";
1481 case SUB_IMM2_8: return "SUB_IMM2_8";
1482 case SUB_IMM2: return "SUB_IMM2";
1483 case SUB_IMM2SX_8: return "SUB_IMM2SX_8";
1484 case XOR_2MEM_8: return "XOR_2MEM_8";
1485 case XOR_2MEM: return "XOR_2MEM";
1486 case XOR_MEM2_8: return "XOR_MEM2_8";
1487 case XOR_MEM2: return "XOR_MEM2";
1488 case XOR_IMM2_8: return "XOR_IMM2_8";
1489 case XOR_IMM2: return "XOR_IMM2";
1490 case XOR_IMM2SX_8: return "XOR_IMM2SX_8";
1491 case INC_8: return "INC_8";
1492 case INC: return "INC";
1493 case DEC_8: return "DEC_8";
1494 case DEC: return "DEC";
1495 case NEG_8: return "NEG_8";
1496 case NEG: return "NEG";
1497 case NOT_8: return "NOT_8";
1498 case NOT: return "NOT";
1499 case XCHG_8: return "XCHG_8";
1500 case XCHG: return "XCHG";
1501 case SETB: return "SETB";
1502 case SETBE: return "SETBE";
1503 case SETL: return "SETL";
1504 case SETLE: return "SETLE";
1505 case SETNB: return "SETNB";
1506 case SETNBE: return "SETNBE";
1507 case SETNL: return "SETNL";
1508 case SETNLE: return "SETNLE";
1509 case SETNO: return "SETNO";
1510 case SETNP: return "SETNP";
1511 case SETNS: return "SETNS";
1512 case SETNZ: return "SETNZ";
1513 case SETP: return "SETP";
1514 case SETS: return "SETS";
1515 case SETZ: return "SETZ";
1516 case SETO: return "SETO";
1517 case STOS_8: return "STOS_8";
1518 case STOS: return "STOS";
1522 return "INVALID_INSTR";