2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Peter Dinda <pdinda@northwestern.edu>
16 * Jack Lange <jarusl@cs.northwestern.edu>
18 * This is free software. You are permitted to use,
19 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
29 #include <palacios/vmm_types.h>
30 /* Pin Based VM Execution Controls */
31 /* INTEL MANUAL: 20-10 vol 3B */
32 #define EXTERNAL_INTERRUPT_EXITING 0x00000001
33 #define NMI_EXITING 0x00000008
34 #define VIRTUAL_NMIS 0x00000020
35 /* Processor Based VM Execution Controls */
36 /* INTEL MANUAL: 20-11 vol. 3B */
37 #define INTERRUPT_WINDOWS_EXIT 0x00000004
38 #define USE_TSC_OFFSETTING 0x00000008
39 #define HLT_EXITING 0x00000080
40 #define INVLPG_EXITING 0x00000200
41 #define MWAIT_EXITING 0x00000400
42 #define RDPMC_EXITING 0x00000800
43 #define RDTSC_EXITING 0x00001000
44 #define CR8_LOAD_EXITING 0x00080000
45 #define CR8_STORE_EXITING 0x00100000
46 #define USE_TPR_SHADOW 0x00200000
47 #define NMI_WINDOW_EXITING 0x00400000
48 #define MOVDR_EXITING 0x00800000
49 #define UNCONDITION_IO_EXITING 0x01000000
50 #define USE_IO_BITMAPS 0x02000000
51 #define USE_MSR_BITMAPS 0x10000000
52 #define MONITOR_EXITING 0x20000000
53 #define PAUSE_EXITING 0x40000000
54 /* VM-Exit Controls */
55 /* INTEL MANUAL: 20-16 vol. 3B */
56 #define HOST_ADDR_SPACE_SIZE 0x00000200
57 #define ACK_IRQ_ON_EXIT 0x00008000
60 VMCS_GUEST_ES_SELECTOR = 0x00000800,
61 VMCS_GUEST_CS_SELECTOR = 0x00000802,
62 VMCS_GUEST_SS_SELECTOR = 0x00000804,
63 VMCS_GUEST_DS_SELECTOR = 0x00000806,
64 VMCS_GUEST_FS_SELECTOR = 0x00000808,
65 VMCS_GUEST_GS_SELECTOR = 0x0000080A,
66 VMCS_GUEST_LDTR_SELECTOR = 0x0000080C,
67 VMCS_GUEST_TR_SELECTOR = 0x0000080E,
68 /* 16 bit host state */
69 VMCS_HOST_ES_SELECTOR = 0x00000C00,
70 VMCS_HOST_CS_SELECTOR = 0x00000C02,
71 VMCS_HOST_SS_SELECTOR = 0x00000C04,
72 VMCS_HOST_DS_SELECTOR = 0x00000C06,
73 VMCS_HOST_FS_SELECTOR = 0x00000C08,
74 VMCS_HOST_GS_SELECTOR = 0x00000C0A,
75 VMCS_HOST_TR_SELECTOR = 0x00000C0C,
76 /* 64 bit control fields */
77 IO_BITMAP_A_ADDR = 0x00002000,
78 IO_BITMAP_A_ADDR_HIGH = 0x00002001,
79 IO_BITMAP_B_ADDR = 0x00002002,
80 IO_BITMAP_B_ADDR_HIGH = 0x00002003,
81 MSR_BITMAPS = 0x00002004,
82 MSR_BITMAPS_HIGH = 0x00002005,
83 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
84 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
85 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
86 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
87 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200A,
88 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200B,
89 VMCS_EXEC_PTR = 0x0000200C,
90 VMCS_EXEC_PTR_HIGH = 0x0000200D,
91 TSC_OFFSET = 0x00002010,
92 TSC_OFFSET_HIGH = 0x00002011,
93 VIRT_APIC_PAGE_ADDR = 0x00002012,
94 VIRT_APIC_PAGE_ADDR_HIGH = 0x00002013,
95 /* 64 bit guest state fields */
96 VMCS_LINK_PTR = 0x00002800,
97 VMCS_LINK_PTR_HIGH = 0x00002801,
98 GUEST_IA32_DEBUGCTL = 0x00002802,
99 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
100 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
101 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002809,
102 /* 32 bit control fields */
103 PIN_VM_EXEC_CTRLS = 0x00004000,
104 PROC_VM_EXEC_CTRLS = 0x00004002,
105 EXCEPTION_BITMAP = 0x00004004,
106 PAGE_FAULT_ERROR_MASK = 0x00004006,
107 PAGE_FAULT_ERROR_MATCH = 0x00004008,
108 CR3_TARGET_COUNT = 0x0000400A,
109 VM_EXIT_CTRLS = 0x0000400C,
110 VM_EXIT_MSR_STORE_COUNT = 0x0000400E,
111 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
112 VM_ENTRY_CTRLS = 0x00004012,
113 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
114 VM_ENTRY_INT_INFO_FIELD = 0x00004016,
115 VM_ENTRY_EXCEPTION_ERROR = 0x00004018,
116 VM_ENTRY_INSTR_LENGTH = 0x0000401A,
117 TPR_THRESHOLD = 0x0000401C,
118 /* 32 bit Read Only data fields */
119 VM_INSTR_ERROR = 0x00004400,
120 EXIT_REASON = 0x00004402,
121 VM_EXIT_INT_INFO = 0x00004404,
122 VM_EXIT_INT_ERROR = 0x00004406,
123 IDT_VECTOR_INFO = 0x00004408,
124 IDT_VECTOR_ERROR = 0x0000440A,
125 VM_EXIT_INSTR_LENGTH = 0x0000440C,
126 VMX_INSTR_INFO = 0x0000440E,
127 /* 32 bit Guest state fields */
128 GUEST_ES_LIMIT = 0x00004800,
129 GUEST_CS_LIMIT = 0x00004802,
130 GUEST_SS_LIMIT = 0x00004804,
131 GUEST_DS_LIMIT = 0x00004806,
132 GUEST_FS_LIMIT = 0x00004808,
133 GUEST_GS_LIMIT = 0x0000480A,
134 GUEST_LDTR_LIMIT = 0x0000480C,
135 GUEST_TR_LIMIT = 0x0000480E,
136 GUEST_GDTR_LIMIT = 0x00004810,
137 GUEST_IDTR_LIMIT = 0x00004812,
138 GUEST_ES_ACCESS = 0x00004814,
139 GUEST_CS_ACCESS = 0x00004816,
140 GUEST_SS_ACCESS = 0x00004818,
141 GUEST_DS_ACCESS = 0x0000481A,
142 GUEST_FS_ACCESS = 0x0000481C,
143 GUEST_GS_ACCESS = 0x0000481E,
144 GUEST_LDTR_ACCESS = 0x00004820,
145 GUEST_TR_ACCESS = 0x00004822,
146 GUEST_INT_STATE = 0x00004824,
147 GUEST_ACTIVITY_STATE = 0x00004826,
148 GUEST_SMBASE = 0x00004828,
149 GUEST_IA32_SYSENTER_CS = 0x0000482A,
150 /* 32 bit host state field */
151 HOST_IA32_SYSENTER_CS = 0x00004C00,
152 /* Natural Width Control Fields */
153 CR0_GUEST_HOST_MASK = 0x00006000,
154 CR4_GUEST_HOST_MASK = 0x00006002,
155 CR0_READ_SHADOW = 0x00006004,
156 CR4_READ_SHADOW = 0x00006006,
157 CR3_TARGET_VALUE_0 = 0x00006008,
158 CR3_TARGET_VALUE_1 = 0x0000600A,
159 CR3_TARGET_VALUE_2 = 0x0000600C,
160 CR3_TARGET_VALUE_3 = 0x0000600E,
161 /* Natural Width Read Only Fields */
162 EXIT_QUALIFICATION = 0x00006400,
167 GUEST_LINEAR_ADDR = 0x0000640A,
168 /* Natural Width Guest State Fields */
169 GUEST_CR0 = 0x00006800,
170 GUEST_CR3 = 0x00006802,
171 GUEST_CR4 = 0x00006804,
172 GUEST_ES_BASE = 0x00006806,
173 GUEST_CS_BASE = 0x00006808,
174 GUEST_SS_BASE = 0x0000680A,
175 GUEST_DS_BASE = 0x0000680C,
176 GUEST_FS_BASE = 0x0000680E,
177 GUEST_GS_BASE = 0x00006810,
178 GUEST_LDTR_BASE = 0x00006812,
179 GUEST_TR_BASE = 0x00006814,
180 GUEST_GDTR_BASE = 0x00006816,
181 GUEST_IDTR_BASE = 0x00006818,
182 GUEST_DR7 = 0x0000681A,
183 GUEST_RSP = 0x0000681C,
184 GUEST_RIP = 0x0000681E,
185 GUEST_RFLAGS = 0x00006820,
186 GUEST_PENDING_DEBUG_EXCS = 0x00006822,
187 GUEST_IA32_SYSENTER_ESP = 0x00006824,
188 GUEST_IA32_SYSENTER_EIP = 0x00006826,
189 /* Natural Width Host State Fields */
190 HOST_CR0 = 0x00006C00,
191 HOST_CR3 = 0x00006C02,
192 HOST_CR4 = 0x00006C04,
193 HOST_FS_BASE = 0x00006C06,
194 HOST_GS_BASE = 0x00006C08,
195 HOST_TR_BASE = 0x00006C0A,
196 HOST_GDTR_BASE = 0x00006C0C,
197 HOST_IDTR_BASE = 0x00006C0E,
198 HOST_IA32_SYSENTER_ESP = 0x00006C10,
199 HOST_IA32_SYSENTER_EIP = 0x00006C12,
200 HOST_RSP = 0x00006C14,
201 HOST_RIP = 0x00006C16,
204 int v3_vmcs_get_field_len(vmcs_field_t field);
205 char* v3_vmcs_get_field_name(vmcs_field_t field);
209 /* VMCS Exit QUALIFICATIONs */
210 struct VMExitIOQual {
211 uint32_t accessSize : 3; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes)
212 uint32_t dir : 1; // (0: Out ;; 1: In)
213 uint32_t string : 1; // (0: not string ;; 1: string)
214 uint32_t REP : 1; // (0: not REP ;; 1: REP)
215 uint32_t opEnc : 1; // (0: DX ;; 1: immediate)
216 uint32_t rsvd : 9; // Set to 0
217 uint32_t port : 16; // IO Port Number
218 } __attribute__((packed));
222 struct VMExitDBGQual {
223 uint32_t B0 : 1; // Breakpoint 0 condition met
224 uint32_t B1 : 1; // Breakpoint 1 condition met
225 uint32_t B2 : 1; // Breakpoint 2 condition met
226 uint32_t B3 : 1; // Breakpoint 3 condition met
227 uint32_t rsvd : 9; // reserved to 0
228 uint32_t BD : 1; // detected DBG reg access
229 uint32_t BS : 1; // cause either single instr or taken branch
230 } __attribute__((packed));
233 struct VMExitTSQual {
234 uint32_t selector : 16; // selector of destination TSS
235 uint32_t rsvd : 14; // reserved to 0
236 uint32_t src : 2; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT)
237 } __attribute__((packed));
239 struct VMExitCRQual {
240 uint32_t crID : 4; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit)
241 uint32_t accessType : 2; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW)
242 uint32_t lmswOpType : 1; // (0: register ; 1: memory)
243 uint32_t rsvd1 : 1; // reserved to 0
244 uint32_t gpr : 4; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
245 uint32_t rsvd2 : 4; // reserved to 0
246 uint32_t lmswSrc : 16; // src data for lmsw
247 } __attribute__((packed));
249 struct VMExitMovDRQual {
250 uint32_t regID : 3; // debug register number
251 uint32_t rsvd1 : 1; // reserved to 0
252 uint32_t dir : 1; // (0: MOV to DR , 1: MOV from DR)
253 uint32_t rsvd2 : 3; // reserved to 0
254 uint32_t gpr : 4; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
255 } __attribute__((packed));
257 /* End Exit Qualifications */
259 /* Exit Vector Info */
260 struct VMExitIntInfo {
261 uint32_t nr : 8; // IRQ number, exception vector, NMI = 2
262 uint32_t type : 3; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
263 uint32_t errorCode : 1; // 1: error Code present
264 uint32_t iret : 1; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
265 uint32_t rsvd : 18; // always 0
266 uint32_t valid : 1; // always 1 if valid
267 } __attribute__((packed));
272 /* End Exit Vector Info */
277 /* Segment Selector Access Rights (32 bits) */
278 /* INTEL Manual: 20-4 vol 3B */
281 struct vmcs_segment_access {
286 uint32_t desc_type : 1;
288 uint32_t present : 1;
291 uint32_t long_mode : 1; // CS only (64 bit active), reserved otherwise
293 uint32_t granularity : 1;
294 uint32_t unusable : 1;
296 } __attribute__((packed));
297 } __attribute__((packed));
298 }__attribute__((packed));
301 struct vmcs_interrupt_state {
302 uint32_t sti_blocking : 1;
303 uint32_t mov_ss_blocking : 1;
304 uint32_t smi_blocking : 1;
305 uint32_t nmi_blocking : 1;
307 } __attribute__((packed));
314 } __attribute__((packed));
317 //uint_t VMCSRead(uint_t tag, void * val);
320 #endif // ! __V3VEE__