palacios/include/palacios/vmcs.h

   1 /*
   2  * This file is part of the Palacios Virtual Machine Monitor developed
   3  * by the V3VEE Project with funding from the United States National
   4  * Science Foundation and the Department of Energy.
   5  *
   6  * The V3VEE Project is a joint project between Northwestern University
   7  * and the University of New Mexico.  You can find out more at
   8  * http://www.v3vee.org
   9  *
  10  * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
  11  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
  12  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
  13  * All rights reserved.
  14  *
  15  * Author: Peter Dinda <pdinda@northwestern.edu>
  16  *         Jack Lange <jarusl@cs.northwestern.edu>
  17  *
  18  * This is free software.  You are permitted to use,
  19  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
  20  */
  21
  22
  23 #ifndef __VMCS_H__
  24 #define __VMCS_H__
  25
  26 #ifdef __V3VEE__
  27
  28
  29 #include <palacios/vmm_types.h>
  30     /* Pin Based VM Execution Controls */
  31     /* INTEL MANUAL: 20-10 vol 3B */
  32 #define   EXT_INTR_EXIT                 0x00000001
  33 #define   NMI_EXIT                      0x00000008
  34 #define   VIRTUAL_NMIS                  0x00000020
  35 /* Processor Based VM Execution Controls */
  36 /* INTEL MANUAL: 20-11 vol. 3B */
  37 #define   INTR_WIN_EXIT                 0x00000004
  38 #define   USE_TSC_OFFSET                0x00000008
  39 #define   HLT_EXIT                      0x00000080
  40 #define   INVLPG_EXIT                   0x00000200
  41 #define   MWAIT_EXIT                    0x00000400
  42 #define   RDPMC_EXIT                    0x00000800
  43 #define   RDTSC_EXIT                    0x00001000
  44 #define   CR8_LOAD_EXIT                 0x00080000
  45 #define   CR8_STORE_EXIT                0x00100000
  46 #define   USE_TPR_SHADOW                0x00200000
  47 #define   NMI_WINDOW_EXIT               0x00400000
  48 #define   MOVDR_EXIT                    0x00800000
  49 #define   UNCOND_IO_EXIT                0x01000000
  50 #define   USE_IO_BITMAPS                0x02000000
  51 #define   USE_MSR_BITMAPS               0x10000000
  52 #define   MONITOR_EXIT                  0x20000000
  53 #define   PAUSE_EXIT                    0x40000000
  54 /* VM-Exit Controls */
  55 /* INTEL MANUAL: 20-16 vol. 3B */
  56 #define   HOST_ADDR_SPACE_SIZE          0x00000200
  57 #define   ACK_IRQ_ON_EXIT               0x00008000
  58
  59 typedef enum {
  60     VMCS_GUEST_ES_SELECTOR       = 0x00000800,
  61     VMCS_GUEST_CS_SELECTOR       = 0x00000802,
  62     VMCS_GUEST_SS_SELECTOR       = 0x00000804,
  63     VMCS_GUEST_DS_SELECTOR       = 0x00000806,
  64     VMCS_GUEST_FS_SELECTOR       = 0x00000808,
  65     VMCS_GUEST_GS_SELECTOR       = 0x0000080A,
  66     VMCS_GUEST_LDTR_SELECTOR     = 0x0000080C,
  67     VMCS_GUEST_TR_SELECTOR       = 0x0000080E,
  68     /* 16 bit host state */
  69     VMCS_HOST_ES_SELECTOR        = 0x00000C00,
  70     VMCS_HOST_CS_SELECTOR        = 0x00000C02,
  71     VMCS_HOST_SS_SELECTOR        = 0x00000C04,
  72     VMCS_HOST_DS_SELECTOR        = 0x00000C06,
  73     VMCS_HOST_FS_SELECTOR        = 0x00000C08,
  74     VMCS_HOST_GS_SELECTOR        = 0x00000C0A,
  75     VMCS_HOST_TR_SELECTOR        = 0x00000C0C,
  76     /* 64 bit control fields */
  77     VMCS_IO_BITMAP_A_ADDR             = 0x00002000,
  78     VMCS_IO_BITMAP_A_ADDR_HIGH        = 0x00002001,
  79     VMCS_IO_BITMAP_B_ADDR             = 0x00002002,
  80     VMCS_IO_BITMAP_B_ADDR_HIGH        = 0x00002003,
  81     VMCS_MSR_BITMAP                   = 0x00002004,
  82     VMCS_MSR_BITMAP_HIGH              = 0x00002005,
  83     VMCS_EXIT_MSR_STORE_ADDR          = 0x00002006,
  84     VMCS_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
  85     VMCS_EXIT_MSR_LOAD_ADDR           = 0x00002008,
  86     VMCS_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
  87     VMCS_ENTRY_MSR_LOAD_ADDR          = 0x0000200A,
  88     VMCS_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200B,
  89     VMCS_EXEC_PTR                     = 0x0000200C,
  90     VMCS_EXEC_PTR_HIGH                = 0x0000200D,
  91     VMCS_TSC_OFFSET                   = 0x00002010,
  92     VMCS_TSC_OFFSET_HIGH              = 0x00002011,
  93     VMCS_VAPIC_ADDR                   = 0x00002012,
  94     VMCS_VAPIC_ADDR_HIGH              = 0x00002013,
  95     /* 64 bit guest state fields */
  96     VMCS_LINK_PTR                     = 0x00002800,
  97     VMCS_LINK_PTR_HIGH                = 0x00002801,
  98     VMCS_GUEST_DBG_CTL               = 0x00002802,
  99     VMCS_GUEST_DBG_CTL_HIGH          = 0x00002803,
 100     VMCS_GUEST_PERF_GLOBAL_CTRL       = 0x00002808,
 101     VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH  = 0x00002809,
 102     /* 32 bit control fields */
 103     VMCS_PIN_CTRLS                    = 0x00004000,
 104     VMCS_PROC_CTRLS                   = 0x00004002,
 105     VMCS_EXCP_BITMAP                  = 0x00004004,
 106     VMCS_PG_FAULT_ERR_MASK            = 0x00004006,
 107     VMCS_PG_FAULT_ERR_MATCH           = 0x00004008,
 108     VMCS_CR3_TGT_CNT                  = 0x0000400A,
 109     VMCS_EXIT_CTRLS                   = 0x0000400C,
 110     VMCS_EXIT_MSR_STORE_CNT           = 0x0000400E,
 111     VMCS_EXIT_MSR_LOAD_CNT            = 0x00004010,
 112     VMCS_ENTRY_CTRLS                  = 0x00004012,
 113     VMCS_ENTRY_MSR_LOAD_CNT           = 0x00004014,
 114     VMCS_ENTRY_INT_INFO               = 0x00004016,
 115     VMCS_ENTRY_EXCP_ERR               = 0x00004018,
 116     VMCS_ENTRY_INSTR_LEN              = 0x0000401A,
 117     VMCS_TPR_THRESHOLD                = 0x0000401C,
 118     /* 32 bit Read Only data fields */
 119     VMCS_INSTR_ERR                    = 0x00004400,
 120     VMCS_EXIT_REASON                  = 0x00004402,
 121     VMCS_EXIT_INT_INFO                = 0x00004404,
 122     VMCS_EXIT_INT_ERR                 = 0x00004406,
 123     VMCS_IDT_VECTOR_INFO              = 0x00004408,
 124     VMCS_IDT_VECTOR_ERR               = 0x0000440A,
 125     VMCS_EXIT_INSTR_LEN               = 0x0000440C,
 126     VMCS_VMX_INSTR_INFO               = 0x0000440E,
 127     /* 32 bit Guest state fields */
 128     VMCS_GUEST_ES_LIMIT               = 0x00004800,
 129     VMCS_GUEST_CS_LIMIT               = 0x00004802,
 130     VMCS_GUEST_SS_LIMIT               = 0x00004804,
 131     VMCS_GUEST_DS_LIMIT               = 0x00004806,
 132     VMCS_GUEST_FS_LIMIT               = 0x00004808,
 133     VMCS_GUEST_GS_LIMIT               = 0x0000480A,
 134     VMCS_GUEST_LDTR_LIMIT             = 0x0000480C,
 135     VMCS_GUEST_TR_LIMIT               = 0x0000480E,
 136     VMCS_GUEST_GDTR_LIMIT             = 0x00004810,
 137     VMCS_GUEST_IDTR_LIMIT             = 0x00004812,
 138     VMCS_GUEST_ES_ACCESS              = 0x00004814,
 139     VMCS_GUEST_CS_ACCESS              = 0x00004816,
 140     VMCS_GUEST_SS_ACCESS              = 0x00004818,
 141     VMCS_GUEST_DS_ACCESS              = 0x0000481A,
 142     VMCS_GUEST_FS_ACCESS              = 0x0000481C,
 143     VMCS_GUEST_GS_ACCESS              = 0x0000481E,
 144     VMCS_GUEST_LDTR_ACCESS            = 0x00004820,
 145     VMCS_GUEST_TR_ACCESS              = 0x00004822,
 146     VMCS_GUEST_INT_STATE              = 0x00004824,
 147     VMCS_GUEST_ACTIVITY_STATE         = 0x00004826,
 148     VMCS_GUEST_SMBASE                 = 0x00004828,
 149     VMCS_GUEST_SYSENTER_CS            = 0x0000482A,
 150     /* 32 bit host state field */
 151     VMCS_HOST_SYSENTER_CS             = 0x00004C00,
 152     /* Natural Width Control Fields */
 153     VMCS_CR0_MASK                     = 0x00006000,
 154     VMCS_CR4_MASK                     = 0x00006002,
 155     VMCS_CR0_READ_SHDW                = 0x00006004,
 156     VMCS_CR4_READ_SHDW                = 0x00006006,
 157     VMCS_CR3_TGT_VAL_0                = 0x00006008,
 158     VMCS_CR3_TGT_VAL_1                = 0x0000600A,
 159     VMCS_CR3_TGT_VAL_2                = 0x0000600C,
 160     VMCS_CR3_TGT_VAL_3                = 0x0000600E,
 161     /* Natural Width Read Only Fields */
 162     VMCS_EXIT_QUAL                    = 0x00006400,
 163     VMCS_IO_RCX                       = 0x00006402,
 164     VMCS_IO_RSI                       = 0x00006404,
 165     VMCS_IO_RDI                       = 0x00006406,
 166     VMCS_IO_RIP                       = 0x00006408,
 167     VMCS_GUEST_LINEAR_ADDR            = 0x0000640A,
 168     /* Natural Width Guest State Fields */
 169     VMCS_GUEST_CR0                    = 0x00006800,
 170     VMCS_GUEST_CR3                    = 0x00006802,
 171     VMCS_GUEST_CR4                    = 0x00006804,
 172     VMCS_GUEST_ES_BASE                = 0x00006806,
 173     VMCS_GUEST_CS_BASE                = 0x00006808,
 174     VMCS_GUEST_SS_BASE                = 0x0000680A,
 175     VMCS_GUEST_DS_BASE                = 0x0000680C,
 176     VMCS_GUEST_FS_BASE                = 0x0000680E,
 177     VMCS_GUEST_GS_BASE                = 0x00006810,
 178     VMCS_GUEST_LDTR_BASE              = 0x00006812,
 179     VMCS_GUEST_TR_BASE                = 0x00006814,
 180     VMCS_GUEST_GDTR_BASE              = 0x00006816,
 181     VMCS_GUEST_IDTR_BASE              = 0x00006818,
 182     VMCS_GUEST_DR7                    = 0x0000681A,
 183     VMCS_GUEST_RSP                    = 0x0000681C,
 184     VMCS_GUEST_RIP                    = 0x0000681E,
 185     VMCS_GUEST_RFLAGS                 = 0x00006820,
 186     VMCS_GUEST_PENDING_DBG_EXCP       = 0x00006822,
 187     VMCS_GUEST_SYSENTER_ESP           = 0x00006824,
 188     VMCS_GUEST_SYSENTER_EIP           = 0x00006826,
 189     /* Natural Width Host State Fields */
 190     VMCS_HOST_CR0                     = 0x00006C00,
 191     VMCS_HOST_CR3                     = 0x00006C02,
 192     VMCS_HOST_CR4                     = 0x00006C04,
 193     VMCS_HOST_FS_BASE                 = 0x00006C06,
 194     VMCS_HOST_GS_BASE                 = 0x00006C08,
 195     VMCS_HOST_TR_BASE                 = 0x00006C0A,
 196     VMCS_HOST_GDTR_BASE               = 0x00006C0C,
 197     VMCS_HOST_IDTR_BASE               = 0x00006C0E,
 198     VMCS_HOST_SYSENTER_ESP            = 0x00006C10,
 199     VMCS_HOST_SYSENTER_EIP            = 0x00006C12,
 200     VMCS_HOST_RSP                     = 0x00006C14,
 201     VMCS_HOST_RIP                     = 0x00006C16,
 202 } vmcs_field_t;
 203
 204 int v3_vmcs_get_field_len(vmcs_field_t field);
 205 const char* v3_vmcs_field_to_str(vmcs_field_t field);
 206 void v3_print_vmcs_guest_state();
 207 void v3_print_vmcs_host_state();
 208
 209
 210 /* VMCS Exit QUALIFICATIONs */
 211 struct VMExitIOQual {
 212     uint32_t accessSize : 3; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes)
 213     uint32_t dir        : 1; // (0: Out ;; 1: In)
 214     uint32_t string     : 1; // (0: not string ;; 1: string)
 215     uint32_t REP        : 1; // (0: not REP ;; 1: REP)
 216     uint32_t opEnc      : 1; // (0: DX ;; 1: immediate)
 217     uint32_t rsvd       : 9; // Set to 0
 218     uint32_t port       : 16; // IO Port Number
 219 } __attribute__((packed));
 220
 221
 222
 223 struct VMExitDBGQual {
 224     uint32_t B0         : 1; // Breakpoint 0 condition met
 225     uint32_t B1         : 1; // Breakpoint 1 condition met
 226     uint32_t B2         : 1; // Breakpoint 2 condition met
 227     uint32_t B3         : 1; // Breakpoint 3 condition met
 228     uint32_t rsvd       : 9; // reserved to 0
 229     uint32_t BD         : 1; // detected DBG reg access
 230     uint32_t BS         : 1; // cause either single instr or taken branch
 231 } __attribute__((packed));
 232
 233
 234 struct VMExitTSQual {
 235     uint32_t selector   : 16; // selector of destination TSS
 236     uint32_t rsvd       : 14; // reserved to 0
 237     uint32_t src        : 2; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT)
 238 } __attribute__((packed));
 239
 240 struct VMExitCRQual {
 241     uint32_t crID       : 4; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit)
 242     uint32_t accessType : 2; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW)
 243     uint32_t lmswOpType : 1; // (0: register ; 1: memory)
 244     uint32_t rsvd1      : 1; // reserved to 0
 245     uint32_t gpr        : 4; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
 246     uint32_t rsvd2      : 4; // reserved to 0
 247     uint32_t lmswSrc    : 16; // src data for lmsw
 248 } __attribute__((packed));
 249
 250 struct VMExitMovDRQual {
 251     uint32_t regID      : 3; // debug register number
 252     uint32_t rsvd1      : 1; // reserved to 0
 253     uint32_t dir        : 1; // (0: MOV to DR , 1: MOV from DR)
 254     uint32_t rsvd2      : 3; // reserved to 0
 255     uint32_t gpr        : 4; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
 256 } __attribute__((packed));
 257
 258 /* End Exit Qualifications */
 259
 260 /* Exit Vector Info */
 261 struct VMExitIntInfo {
 262     uint32_t nr         : 8; // IRQ number, exception vector, NMI = 2
 263     uint32_t type       : 3; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
 264     uint32_t errorCode  : 1; // 1: error Code present
 265     uint32_t iret       : 1; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
 266     uint32_t rsvd       : 18; // always 0
 267     uint32_t valid      : 1; // always 1 if valid
 268 } __attribute__((packed));
 269
 270
 271
 272
 273 /*  End Exit Vector Info */
 274
 275
 276
 277
 278 /* Segment Selector Access Rights (32 bits) */
 279 /* INTEL Manual: 20-4 vol 3B */
 280
 281
 282 struct vmcs_segment_access {
 283     union {
 284         uint32_t value;
 285         struct {
 286             uint32_t    type        : 4;
 287             uint32_t    desc_type   : 1;
 288             uint32_t    dpl         : 2;
 289             uint32_t    present     : 1;
 290             uint32_t    rsvd1       : 4;
 291             uint32_t    avail       : 1;
 292             uint32_t    long_mode   : 1; // CS only (64 bit active), reserved otherwise
 293             uint32_t    db          : 1;
 294             uint32_t    granularity : 1;
 295             uint32_t    unusable    : 1;
 296             uint32_t    rsvd2       : 15;
 297         } __attribute__((packed));
 298     } __attribute__((packed));
 299 }__attribute__((packed));
 300
 301
 302 struct vmcs_interrupt_state {
 303     uint32_t    sti_blocking    : 1;
 304     uint32_t    mov_ss_blocking : 1;
 305     uint32_t    smi_blocking    : 1;
 306     uint32_t    nmi_blocking    : 1;
 307     uint32_t    rsvd1           : 28;
 308 } __attribute__((packed));
 309
 310
 311
 312 struct vmcs_data {
 313     uint32_t revision ;
 314     uint32_t abort    ;
 315 } __attribute__((packed));
 316
 317
 318 //uint_t VMCSRead(uint_t tag, void * val);
 319
 320
 321 #endif // ! __V3VEE__
 322
 323
 324 #endif