palacios/include/palacios/svm.h

   1 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
   2 /* (c) 2008, The V3VEE Project <http://www.v3vee.org> */
   3
   4
   5 #ifndef __SVM_H
   6 #define __SVM_H
   7
   8
   9
  10
  11 #ifdef __V3VEE__
  12
  13 #include <palacios/vmm.h>
  14
  15
  16 #include <palacios/vmcb.h>
  17 #include <palacios/vmm_util.h>
  18
  19 #define CPUID_FEATURE_IDS 0x80000001
  20 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
  21
  22 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
  23 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
  24 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_np  0x00000001
  25
  26
  27 #define EFER_MSR                 0xc0000080
  28 #define EFER_MSR_svm_enable      0x00001000
  29
  30 /************/
  31 /* SVM MSRs */
  32 /************/
  33 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
  34 /************/
  35
  36 // SVM VM_CR MSR
  37 #define SVM_VM_CR_MSR             0xc0010114
  38 #define SVM_VM_CR_MSR_dpd         0x00000001
  39 #define SVM_VM_CR_MSR_r_init      0x00000002
  40 #define SVM_VM_CR_MSR_dis_a20m    0x00000004
  41 #define SVM_VM_CR_MSR_lock        0x00000008
  42 #define SVM_VM_CR_MSR_svmdis      0x00000010
  43
  44 #define SVM_IGNNE_MSR             0xc0010115
  45
  46 // SMM Signal Control Register
  47 #define SVM_SMM_CTL_MSR           0xc0010116
  48 #define SVM_SMM_CTL_MSR_dismiss   0x00000001
  49 #define SVM_SMM_CTL_MSR_enter     0x00000002
  50 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
  51 #define SVM_SMM_CTL_MSR_exit      0x00000008
  52 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
  53
  54 #define SVM_VM_HSAVE_PA_MSR      0xc0010117
  55
  56 #define SVM_KEY_MSR              0xc0010118
  57
  58 /******/
  59
  60
  61
  62
  63 #define SVM_HANDLER_SUCCESS   0x0
  64 #define SVM_HANDLER_ERROR     0x1
  65 #define SVM_HANDLER_HALT      0x2
  66
  67
  68
  69 void Init_SVM(struct vmm_ctrl_ops * vmm_ops);
  70 int is_svm_capable();
  71
  72 #endif
  73
  74
  75
  76 #endif