palacios/include/palacios/svm.h

   1 #ifndef __SVM_H
   2 #define __SVM_H
   3
   4
   5 #include <palacios/vmm.h>
   6
   7
   8 #ifdef __V3VEE__
   9
  10 #include <palacios/vmcb.h>
  11 #include <palacios/vmm_util.h>
  12
  13 #define CPUID_FEATURE_IDS 0x80000001
  14 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
  15
  16 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
  17 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
  18 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_np  0x00000001
  19
  20
  21 #define EFER_MSR                 0xc0000080
  22 #define EFER_MSR_svm_enable      0x00001000
  23
  24 /************/
  25 /* SVM MSRs */
  26 /************/
  27 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
  28 /************/
  29
  30 // SVM VM_CR MSR
  31 #define SVM_VM_CR_MSR             0xc0010114
  32 #define SVM_VM_CR_MSR_dpd         0x00000001
  33 #define SVM_VM_CR_MSR_r_init      0x00000002
  34 #define SVM_VM_CR_MSR_dis_a20m    0x00000004
  35 #define SVM_VM_CR_MSR_lock        0x00000008
  36 #define SVM_VM_CR_MSR_svmdis      0x00000010
  37
  38 #define SVM_IGNNE_MSR             0xc0010115
  39
  40 // SMM Signal Control Register
  41 #define SVM_SMM_CTL_MSR           0xc0010116
  42 #define SVM_SMM_CTL_MSR_dismiss   0x00000001
  43 #define SVM_SMM_CTL_MSR_enter     0x00000002
  44 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
  45 #define SVM_SMM_CTL_MSR_exit      0x00000008
  46 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
  47
  48 #define SVM_VM_HSAVE_PA_MSR      0xc0010117
  49
  50 #define SVM_KEY_MSR              0xc0010118
  51
  52 /******/
  53
  54
  55
  56
  57 #define SVM_HANDLER_SUCCESS   0x0
  58 #define SVM_HANDLER_ERROR     0x1
  59 #define SVM_HANDLER_HALT      0x2
  60
  61 #endif
  62
  63
  64 void Init_SVM(struct vmm_ctrl_ops * vmm_ops);
  65 int is_svm_capable();
  66
  67
  68
  69
  70 #endif