palacios/include/palacios/svm.h

   1 /* Northwestern University */
   2 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
   3
   4 #ifndef __SVM_H
   5 #define __SVM_H
   6
   7
   8 #include <palacios/vmm.h>
   9
  10
  11 #ifdef __V3VEE__
  12
  13 #include <palacios/vmcb.h>
  14 #include <palacios/vmm_util.h>
  15
  16 #define CPUID_FEATURE_IDS 0x80000001
  17 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
  18
  19 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
  20 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
  21 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_np  0x00000001
  22
  23
  24 #define EFER_MSR                 0xc0000080
  25 #define EFER_MSR_svm_enable      0x00001000
  26
  27 /************/
  28 /* SVM MSRs */
  29 /************/
  30 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
  31 /************/
  32
  33 // SVM VM_CR MSR
  34 #define SVM_VM_CR_MSR             0xc0010114
  35 #define SVM_VM_CR_MSR_dpd         0x00000001
  36 #define SVM_VM_CR_MSR_r_init      0x00000002
  37 #define SVM_VM_CR_MSR_dis_a20m    0x00000004
  38 #define SVM_VM_CR_MSR_lock        0x00000008
  39 #define SVM_VM_CR_MSR_svmdis      0x00000010
  40
  41 #define SVM_IGNNE_MSR             0xc0010115
  42
  43 // SMM Signal Control Register
  44 #define SVM_SMM_CTL_MSR           0xc0010116
  45 #define SVM_SMM_CTL_MSR_dismiss   0x00000001
  46 #define SVM_SMM_CTL_MSR_enter     0x00000002
  47 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
  48 #define SVM_SMM_CTL_MSR_exit      0x00000008
  49 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
  50
  51 #define SVM_VM_HSAVE_PA_MSR      0xc0010117
  52
  53 #define SVM_KEY_MSR              0xc0010118
  54
  55 /******/
  56
  57
  58
  59
  60 #define SVM_HANDLER_SUCCESS   0x0
  61 #define SVM_HANDLER_ERROR     0x1
  62 #define SVM_HANDLER_HALT      0x2
  63
  64 #endif
  65
  66
  67 void Init_SVM(struct vmm_ctrl_ops * vmm_ops);
  68 int is_svm_capable();
  69
  70
  71
  72
  73 #endif