palacios/include/geekos/svm.h

   1 #ifndef __SVM_H
   2 #define __SVM_H
   3
   4 #include <geekos/screen.h>
   5 #include <geekos/serial.h>
   6
   7
   8 #define CPUID_FEATURE_IDS 0x80000001
   9 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
  10
  11 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
  12 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
  13
  14
  15 #define EFER_MSR                 0xc0000080
  16 #define EFER_MSR_svm_enable      0x00001000
  17
  18 /************/
  19 /* SVM MSRs */
  20 /************/
  21 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
  22 /************/
  23
  24 /* SVM VM_CR MSR */
  25 #define SVM_VM_CR_MSR             0xc0010114
  26 #define SVM_VM_CR_MSR_dpd         0x00000001
  27 #define SVM_VM_CR_MSR_r_init      0x00000002
  28 #define SVM_VM_CR_MSR_dis_a20m    0x00000004
  29 #define SVM_VM_CR_MSR_lock        0x00000008
  30 #define SVM_VM_CR_MSR_svmdis      0x00000010
  31
  32 #define SVM_IGNNE_MSR             0xc0010115
  33
  34 /* SMM Signal Control Register */
  35 #define SVM_SMM_CTL_MSR           0xc0010116
  36 #define SVM_SMM_CTL_MSR_dismiss   0x00000001
  37 #define SVM_SMM_CTL_MSR_enter     0x00000002
  38 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
  39 #define SVM_SMM_CTL_MSR_exit      0x00000008
  40 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
  41
  42 #define SVM_VM_HSAVE_PA_MSR      0xc0010117
  43 #define SVM_KEY_MSR              0xc0010118
  44
  45 /* ** */
  46
  47
  48 void Init_SVM();
  49 int is_svm_capable();
  50
  51
  52
  53
  54 #endif