palacios/include/geekos/svm.h

   1 #ifndef __SVM_H
   2 #define __SVM_H
   3
   4 #include <geekos/vmm.h>
   5
   6 #define CPUID_FEATURE_IDS 0x80000001
   7 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
   8
   9 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
  10 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
  11
  12
  13 #define EFER_MSR                 0xc0000080
  14 #define EFER_MSR_svm_enable      0x00001000
  15
  16 /************/
  17 /* SVM MSRs */
  18 /************/
  19 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
  20 /************/
  21
  22 /* SVM VM_CR MSR */
  23 #define SVM_VM_CR_MSR             0xc0010114
  24 #define SVM_VM_CR_MSR_dpd         0x00000001
  25 #define SVM_VM_CR_MSR_r_init      0x00000002
  26 #define SVM_VM_CR_MSR_dis_a20m    0x00000004
  27 #define SVM_VM_CR_MSR_lock        0x00000008
  28 #define SVM_VM_CR_MSR_svmdis      0x00000010
  29
  30 #define SVM_IGNNE_MSR             0xc0010115
  31
  32 /* SMM Signal Control Register */
  33 #define SVM_SMM_CTL_MSR           0xc0010116
  34 #define SVM_SMM_CTL_MSR_dismiss   0x00000001
  35 #define SVM_SMM_CTL_MSR_enter     0x00000002
  36 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
  37 #define SVM_SMM_CTL_MSR_exit      0x00000008
  38 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
  39
  40 #define SVM_VM_HSAVE_PA_MSR      0xc0010117
  41 #define SVM_KEY_MSR              0xc0010118
  42
  43 /* ** */
  44
  45
  46 void Init_SVM();
  47 int is_svm_capable();
  48
  49
  50
  51
  52 #endif