2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2012, NWU EECS 441 Transactional Memory Team
11 * Copyright (c) 2012, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Maciek Swiech <dotpyfe@u.northwestern.edu>
15 * Marcel Flores <marcel-flores@u.northwestern.edu>
16 * Zachary Bischof <zbischof@u.northwestern.edu>
17 * Kyle C. Hale <kh@u.northwestern.edu>
19 * This is free software. You are permitted to use,
20 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
23 RTM Implementation Wishlist (roughly in order of priority)
24 Kyle Hale, Maciek Swiech 2014
26 From Intel Architecture Instruction Set Extensions Programming Reference, Section 8.3, p.8-6
27 link: http://software.intel.com/sites/default/files/m/9/2/3/41604
29 - on XABORT / abort RAX needs to be set with the reason
30 - architectural registers need to be saved / restored
31 - exceptions that misuse of TSX instructions can raise
32 - abort on interrupts, asynchronous events
33 - abort on CPUID, PAUSE
34 - abort on non-writeback memory ops, including ifetches to uncacheable mem
35 - RTM-debugger support
37 - parameterized cache model, for generating hardware configuration-based aborts
39 - to be able to model specific implementations, add options (runtime or compiletime) to abort on:
40 * x86/mmx state changes, (also fxstor, fxsave),
41 * cli, sti, popfd, popfq, clts
42 * mov to segment regs, pop segment regs, lds, les, lfs, lgs, lss, swapgs, wrfsbase, wrgsbase, lgdt, sgdt, lidt, sidt, lldt, sldt, ltr,
43 str, far call, far jmp, far ret, far iret, mov to DRx, mov to cr0-4, cr8 lmsw
44 * sysenter, syscall, sysexit, sysret
45 * clflush, invd, wbinvd, invlpg, invpcid
46 * memory instructions with temporal hints (e.g. movntdqa)
47 * xsave, xsaveopt, xrstor
48 * interrupts: INTn, INTO
49 * IO: in, ins, rep ins, out, outs, rep outs, and variants
52 * ud2, rsm, rdmsr, wrmsr, hlt, monitor, mwait, xsetbv, vzeroupper, maskmovq, v/maskmovdqu
56 * We claim that we can have a single, shared "cache"-like box
57 * that handles all writes and reads when TM is on on any core. The
58 * idea is that if TM is on on any core, we redirect reads/writes
59 * that we get to the box, and it records them internally for
60 * future playback, and tells us whether an abort condition has
63 * error = handle_start_tx(boxstate,vcorenum);
64 * error = handle_abort(boxstate,vcorenum);
65 * error = handle_commit(boxstate,vcorenum);
67 * should_abort = handle_write(boxstate, vcorenum, physaddr, data, datalen);
68 * should_abort = handle_read(boxstate, vcorenum,physaddr, *data, datalen);
73 * enum {READ,WRITE,BEGIN,ABORT,END} op;
80 * struct cache_model {
81 * void *init(xml spec); // make a cache, return ptr to state
82 * int write(void *priv, physaddr, datalen, int (*change_cb(int core,
83 * physaddrstart, len));
84 * // similiar for read
86 * // Idea is that we pass writes to cache model, it calls us back to say which
87 * lines on which cores have changed
92 * struct cache_model *model; //
93 * lock_t global_lock; // any handle_* func acquires this first
95 * uint64_t numtransactionsactive;
99 * int handle_write(box,vcore,physaddr,data,datalen) {
103 #ifndef __TRANS_MEM_H__
104 #define __TRANS_MEM_H__
106 #include <palacios/vmm_lock.h>
107 #include <palacios/vmcb.h>
108 #include <palacios/vmm_paging.h>
112 #define TM_KICKBACK_CALL 0x1337
114 #define HTABLE_SEARCH(h, k) ({ addr_t ret; v3_lock(h##_lock); ret = v3_htable_search((h), (k)); v3_unlock(h##_lock); ret; })
115 #define HTABLE_INSERT(h, k, v) ({ addr_t ret; v3_lock(h##_lock); ret = v3_htable_insert((h), (k), (addr_t)(v)); v3_unlock(h##_lock); ret; })
117 #define INSTR_INJECT_LEN 10
118 #define INSTR_BUF_SZ 15
119 #define ERR_STORE_MUST_ABORT -2
120 #define ERR_STORE_FAIL -1
121 #define ERR_DECODE_FAIL -1
122 #define ERR_TRANS_FAULT_FAIL 0
123 #define TRANS_FAULT_OK 1
124 #define TRANS_HCALL_FAIL -1
125 #define TRANS_HCALL_OK 0
127 /* conflict checking codes */
128 #define ERR_CHECK_FAIL -1
129 #define CHECK_MUST_ABORT -2
130 #define CHECK_IS_CONFLICT 1
131 #define CHECK_NO_CONFLICT 0
133 /* RTM instruction handling */
134 #define XBEGIN_INSTR_LEN 0x6
135 #define XEND_INSTR_LEN 0x3
136 #define XABORT_INSTR_LEN 0x3
137 #define XTEST_INSTR_LEN 0x3
140 struct v3_tm_access_type {
143 } __attribute__((packed));
145 struct v3_ctxt_tuple {
149 } __attribute__((packed));
151 /* 441-tm: Are we currently in a transaction */
157 /* 441-tm: Current state of the transaction state machine */
165 typedef enum v3_tm_op {
170 struct v3_trans_mem {
171 /* current transaction */
174 /* 441-tm: linked list to store core's reads and writes */
175 struct list_head trans_r_list;
176 struct list_head trans_w_list;
178 /* 441-tm: hash tables of addresses */
179 struct hashtable * addr_ctxt; // records the core transaction context at time of address use
180 v3_lock_t addr_ctxt_lock;
181 uint64_t addr_ctxt_entries;
183 struct hashtable * access_type; // hashes addr:corenum:t_num for each address use
184 v3_lock_t access_type_lock;
185 uint64_t access_type_entries;
187 /* 441-tm: lets remember things about the next instruction */
188 uint8_t dirty_instr_flag;
191 uchar_t dirty_instr[15];
194 enum TM_MODE_E TM_MODE;
195 enum TM_STATE_E TM_STATE;
198 struct shadow_page_data * staging_page;
200 /* 441-tm: Remember the failsafe addr */
203 /* 441-tm: Save the rax we are about to ruin */
204 v3_reg_t clobbered_rax;
213 uint64_t entry_exits;
216 struct cache_box * box;
218 struct guest_info * ginfo;
225 enum TM_MODE_E TM_MODE;
226 uint64_t cores_active;
228 uint64_t * last_trans;
234 struct list_head lt_node;
237 // called from #PF handler, stages entries, catches reads / writes
238 addr_t v3_handle_trans_mem_fault(struct guest_info *core,
242 // restores instruction after core->rip
243 int v3_restore_dirty_instr(struct guest_info *core);
245 // restores instruction after core->rip
246 int v3_restore_abort_instr(struct guest_info *core);
248 // handles abort cleanup, called from INT/EXCP or XABORT
249 int v3_handle_trans_abort(struct guest_info *core);
251 // record a memory access in hashes
252 int tm_record_access (struct v3_trans_mem * tm,
256 // garbage collect hash recordings
257 int tm_hash_gc (struct v3_trans_mem * tm);
259 // check address for conflicts
260 int tm_check_conflict(struct v3_vm_info * vm_info,
266 // increment transaction number
267 int v3_tm_inc_tnum(struct v3_trans_mem * tm);
270 /* exception-related functions */
271 int v3_tm_handle_exception(struct guest_info * info, addr_t exit_code);
273 void v3_tm_set_excp_intercepts(vmcb_ctrl_t * ctrl_area);
275 void v3_tm_check_intr_state(struct guest_info * info,
276 vmcb_ctrl_t * guest_ctrl,
277 vmcb_saved_state_t * guest_state);
280 /* paging-related functions */
281 int v3_tm_handle_pf_64 (struct guest_info * info,
282 pf_error_t error_code,
284 addr_t * page_to_use);
286 void v3_tm_handle_usr_tlb_miss(struct guest_info * info,
287 pf_error_t error_code,
291 void v3_tm_handle_read_fault(struct guest_info * info,
292 pf_error_t error_code,
293 pte64_t * shadow_pte);
295 #include <palacios/vmm_decoder.h>
297 /* decoding-related functions */
298 int v3_tm_decode_rtm_instrs(struct guest_info * info,
300 struct x86_instr * instr);