Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


probably should include the header file.... mmmph...
[palacios.git] / palacios / include / devices / pci.h
1 /* 
2  * This file is part of the Palacios Virtual Machine Monitor developed
3  * by the V3VEE Project with funding from the United States National 
4  * Science Foundation and the Department of Energy.  
5  *
6  * The V3VEE Project is a joint project between Northwestern University
7  * and the University of New Mexico.  You can find out more at 
8  * http://www.v3vee.org
9  *
10  * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11  * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
12  * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org> 
13  * All rights reserved.
14  *
15  * Author:  Lei Xia <lxia@northwestern.edu>
16  *             Chang Seok Bae <jhuell@gmail.com>
17  *
18  * This is free software.  You are permitted to use,
19  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20  */
21
22 #ifndef __DEVICES_PCI_H__
23 #define __DEVICES_PCI_H__
24
25 #ifdef __V3VEE__
26
27 #include <palacios/vm_dev.h>
28 #include <palacios/vmm_types.h>
29 #include <palacios/vmm_rbtree.h>
30
31 #include <devices/pci_types.h>
32
33
34 typedef enum {PCI_BAR_IO, PCI_BAR_MEM16, PCI_BAR_MEM32, PCI_BAR_MEM64_LOW, PCI_BAR_MEM64_HIGH, PCI_BAR_NONE} pci_bar_type_t;
35
36 typedef enum {PCI_STD_DEVICE, PCI_TO_PCI_BRIDGE, PCI_CARDBUS, PCI_MULTIFUNCTION} pci_device_type_t;
37
38 typedef enum { PCI_CLASS_PRE2 = 0x00, 
39                PCI_CLASS_STORAGE = 0x01, 
40                PCI_CLASS_NETWORK = 0x02,
41                PCI_CLASS_DISPLAY = 0x03,
42                PCI_CLASS_MMEDIA = 0x04,
43                PCI_CLASS_MEMORY = 0x05,
44                PCI_CLASS_BRIDGE = 0x06,
45                PCI_CLASS_COMM_CTRL = 0x07,
46                PCI_CLASS_BASE_PERIPH = 0x08,
47                PCI_CLASS_INPUT = 0x09, 
48                PCI_CLASS_DOCK = 0x0a,
49                PCI_CLASS_PROC = 0x0b, 
50                PCI_CLASS_SERIAL = 0x0c,
51                PCI_CLASS_MISC = 0xff } pci_class_t;
52
53 typedef enum { PCI_STORAGE_SUBCLASS_SCSI = 0x00,
54                PCI_STORAGE_SUBCLASS_IDE = 0x01,
55                PCI_STORAGE_SUBCLASS_FLOPPY = 0x02,
56                PCI_STORAGE_SUBCLASS_IPI = 0x03,
57                PCI_STORAGE_SUBCLASS_RAID = 0x04,
58                PCI_STORAGE_SUBCLASS_OTHER = 0x80 } pci_storage_subclass_t;
59
60
61
62 typedef enum { PCI_NET_SUBCLASS_ETHER = 0x00,
63                PCI_NET_SUBCLASS_TOKRING = 0x01,
64                PCI_NET_SUBCLASS_FDDI = 0x02,
65                PCI_NET_SUBCLASS_ATM = 0x03,
66                PCI_NET_SUBCLASS_OTHER = 0x80 } pci_network_subclass_t;
67
68 typedef enum { PCI_DISPLAY_SUBCLASS_VGA = 0x00,
69                PCI_DISPLAY_SUBCLASS_XGA = 0x01,
70                PCI_DISPLAY_SUBCLASS_OTHER = 0x80 } pci_display_subclass_t;
71
72 typedef enum { PCI_MMEDIA_SUBCLASS_VIDEO = 0x00,
73                PCI_MMEDIA_SUBCLASS_AUDIO = 0x01,
74                PCI_MMEDIA_SUBCLASS_OTHER = 0x80 } pci_multimedia_subclass_t;
75                
76 typedef enum { PCI_MEM_SUBCLASS_RAM = 0x00, 
77                PCI_MEM_SUBCLASS_FLASH = 0x01,
78                PCI_MEM_SUBCLASS_OTHER = 0x80 } pci_memory_subclass_t;
79
80 typedef enum { PCI_BRIDGE_SUBCLASS_HOST_PCI = 0x00,
81                PCI_BRIDGE_SUBCLASS_PCI_ISA = 0x01,
82                PCI_BRIDGE_SUBCLASS_PCI_EISA = 0x02,
83                PCI_BRIDGE_SUBCLASS_PCI_MICRO = 0x03,
84                PCI_BRIDGE_SUBCLASS_PCI_PCI = 0x04,
85                PCI_BRIDGE_SUBCLASS_PCI_PCMCIA = 0x05,
86                PCI_BRIDGE_SUBCLASS_PCI_NUBUS = 0x06,
87                PCI_BRIDGE_SUBCLASS_PCI_CARDBUS = 0x07,
88                PCI_BRIDGE_SUBCLASS_PCI_OTHER = 0x80 } pci_bridge_subclass_t;
89
90 // For the rest of the subclass codes see:
91 // http://www.acm.uiuc.edu/sigops/roll_your_own/7.c.1.html
92
93 #define PCI_AUTO_DEV_NUM (-1)
94
95 struct pci_device;
96
97 struct v3_pci_bar {
98     pci_bar_type_t type;
99     
100     union {
101         struct {
102             int num_pages;
103             addr_t default_base_addr;
104             int (*mem_read)(addr_t guest_addr, void * dst, uint_t length, void * private_data);
105             int (*mem_write)(addr_t guest_addr, void * src, uint_t length, void * private_data);
106         };
107
108         struct {
109             int num_ports;
110             uint16_t default_base_port;
111             int (*io_read)(ushort_t port, void * dst, uint_t length, struct vm_device * dev);
112             int (*io_write)(ushort_t port, void * src, uint_t length, struct vm_device * dev);
113         };
114     };
115
116     // Internal PCI data
117     uint32_t val;
118     int updated;
119     uint32_t mask;
120 };
121
122
123 #define PCI_IO_BASE(bar_val) (bar_val & 0xfffffffc)
124 #define PCI_MEM32_BASE(bar_val) (bar_val & 0xfffffff0)
125
126 struct pci_device {
127
128     union {
129         uint8_t config_space[256];
130
131         struct {
132             struct pci_config_header config_header;
133             uint8_t config_data[192];
134         } __attribute__((packed));
135     } __attribute__((packed));
136
137     struct v3_pci_bar bar[6];
138
139     struct rb_node dev_tree_node;
140
141     uint_t bus_num;
142
143     union {
144         uint8_t devfn;
145         struct {
146             uint8_t fn_num       : 3;
147             uint8_t dev_num      : 5;
148         } __attribute__((packed));
149     } __attribute__((packed));
150
151     char name[64];
152
153     struct vm_device * vm_dev;  //the corresponding virtual device
154
155     int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length);
156
157     int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled);
158     int (*ext_rom_update)(struct pci_device *pci_dev);
159
160     int ext_rom_update_flag;
161     int bar_update_flag;
162
163     void * priv_data;
164 };
165
166
167
168 struct vm_device * v3_create_pci();
169
170 struct pci_device * 
171 v3_pci_register_device(struct vm_device * pci,
172                        pci_device_type_t dev_type, 
173                        int bus_num,
174                        int dev_num,
175                        int fn_num,
176                        const char * name,
177                        struct v3_pci_bar * bars,
178                        int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
179                        int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
180                        int (*ext_rom_update)(struct pci_device *pci_dev),
181                        struct vm_device * dev);
182
183
184 #endif
185
186 #endif
187