Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


Merge branch 'devel'
[palacios.git] / kitten / include / arch-x86_64 / cpuinfo.h
1 /**
2  * Portions derived from Linux include/asm-x86_64/processor.h
3  * Copyright (C) 1994 Linus Torvalds
4  */
5
6 #ifndef _X86_64_CPUINFO_H
7 #define _X86_64_CPUINFO_H
8
9 #include <arch/cpufeature.h>
10
11 /**
12  * arch_cpuinfo.x86_cache_size first dimension indicies.
13  * and
14  * arch_cpuinfo.x86_tlbsize first dimension indicies.
15  */
16 #define INST    0       /* Instruction */
17 #define DATA    1       /* Data */
18 #define UNIF    2       /* Unified Instruction and Data */
19
20 /**
21  * arch_cpuinfo.x86_cache_size second dimension indices.
22  * and
23  * arch_cpuinfo.x86_tlbsize second dimension indices.
24  */
25 #define L1      0
26 #define L2      1
27 #define L3      2
28
29 /**
30  * arch_cpuinfo.x86_tlbsize third dimension indices.
31  */
32 #define PAGE_4KB        0
33 #define PAGE_2MB        1
34 #define PAGE_1GB        2
35
36 /**
37  * Architecture specific CPU information and hardware bug flags.
38  * CPU info is kept separately for each CPU.
39  */
40 struct arch_cpuinfo {
41     uint8_t  x86_vendor;            /* CPU vendor */
42     uint8_t  x86_family;            /* CPU family */
43     uint8_t  x86_model;             /* CPU model */
44     uint8_t  x86_stepping;          /* CPU stepping */
45     uint32_t x86_capability[NCAPINTS]; /* optional CPU features */
46     char     x86_vendor_id[16];     /* Vendor ID string */
47     char     x86_model_id[64];      /* Model/Brand ID string */
48     uint16_t x86_cache_size[3][3];  /* [I|D|U][LEVEL], in KB */
49     uint16_t x86_cache_line[3][3];  /* [I|D|U][LEVEL], in bytes */
50     int      x86_clflush_size;      /* In bytes */
51     uint16_t x86_tlb_size[3][2][3]; /* [I|D|U][LEVEL][PAGE_SIZE], in #entries */
52     uint8_t  x86_virt_bits;         /* Bits of virt address space */
53     uint8_t  x86_phys_bits;         /* Bits of phys address space */
54     uint8_t  x86_pkg_cores;         /* Number of cores in this CPU's package */
55     uint32_t x86_power;             /* Power management features */
56     uint32_t cpuid_level;           /* Max supported CPUID level */
57     uint32_t extended_cpuid_level;  /* Max extended CPUID func supported */
58     uint32_t cur_cpu_khz;           /* Current CPU freq. in KHz */
59     uint32_t max_cpu_khz;           /* Maximum CPU freq. in KHz */
60     uint32_t min_cpu_khz;           /* Minimum CPU freq. in KHz */
61     uint32_t tsc_khz;               /* Time stamp counter freq. in KHz */
62     uint32_t lapic_khz;             /* Local APIC bus freq. in KHz */
63     uint8_t  apic_id;               /* Local APIC ID, phys CPU ID */
64     uint8_t  initial_lapic_id;      /* As reported by CPU ID */
65 };
66
67 extern struct cpuinfo boot_cpu_data;
68
69 struct cpuinfo;
70 extern void print_arch_cpuinfo(struct cpuinfo *);
71 extern void early_identify_cpu(struct cpuinfo *);
72
73 #endif