#define SX_EXCEPTION 0x1e
-typedef enum {INVALID_INTR, EXTERNAL_IRQ, NMI, EXCEPTION, SOFTWARE, VIRTUAL} intr_types_t;
+typedef enum {INVALID_INTR, EXTERNAL_IRQ, NMI, EXCEPTION, SOFTWARE, VIRTUAL} intr_type_t;
struct guest_info;
struct vm_intr {
+
+ /* We need to rework the exception state, to handle stacking */
uint_t excp_pending;
uint_t excp_num;
+ uint_t excp_error_code_valid : 1;
uint_t excp_error_code;
struct intr_ctrl_ops * controller;
void set_intr_controller(struct guest_info * info, struct intr_ctrl_ops * ops, void * state);
int raise_exception(struct guest_info * info, uint_t excp);
+int raise_exception_with_error(struct guest_info * info, uint_t excp, uint_t error_code);
+
+int intr_pending(struct guest_info * info);
+uint_t get_intr_number(struct guest_info * info);
+intr_type_t get_intr_type(struct guest_info * info);
-int intr_pending(struct vm_intr * intr);
-uint_t get_intr_number(struct vm_intr * intr);
-intr_types_t get_intr_type(struct vm_intr * intr);
+int injecting_intr(struct guest_info * info, uint_t intr_num, intr_type_t type);
/*
int start_irq(struct vm_intr * intr);
for (i = 0; i < 16; i++) {
if (i <= 7) {
if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
- state->master_isr |= (0x1 << i);
+ //state->master_isr |= (0x1 << i);
// reset the irr
- state->master_irr &= ~(0x1 << i);
+ //state->master_irr &= ~(0x1 << i);
PrintDebug("IRQ: %d, icw2: %x\n", i, state->master_icw2);
return i + state->master_icw2;
}
} else {
if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
- state->slave_isr |= (0x1 << (i - 8));
- state->slave_irr &= ~(0x1 << (i - 8));
+ //state->slave_isr |= (0x1 << (i - 8));
+ //state->slave_irr &= ~(0x1 << (i - 8));
return (i - 8) + state->slave_icw2;
}
}
}
+
+
+
static int pic_begin_irq(void * private_data, int irq) {
+ struct pic_internal * state = (struct pic_internal*)private_data;
+
+ if (irq <= 7) {
+ if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
+ state->master_isr |= (0x1 << irq);
+ state->master_irr &= ~(0x1 << irq);
+ }
+ } else {
+ state->slave_isr |= (0x1 << (irq - 8));
+ state->slave_irr &= ~(0x1 << (irq - 8));
+ }
return 0;
}