}
#ifdef V3_CONFIG_CHECKPOINT
+
+#include <palacios/vmm_sprintf.h>
+
+#define KEY_MAX 128
+#define MAKE_KEY(x) snprintf(key,KEY_MAX,"PIT_CH%d_%s",i,x)
+
static int pit_save(struct v3_chkpt_ctx * ctx, void * private_data) {
struct pit * pit_state = (struct pit *)private_data;
-
- V3_CHKPT_SAVE_AUTOTAG(ctx, pit_state->pit_counter,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, pit_state->pit_reload,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, pit_state->ch_0,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, pit_state->ch_1,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, pit_state->ch_2,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, pit_state->speaker,savefailout);
+ int i;
+ char key[KEY_MAX];
+
+ V3_CHKPT_SAVE(ctx, "PIT_COUNTER", pit_state->pit_counter,savefailout);
+ V3_CHKPT_SAVE(ctx, "PIT_RELOAD", pit_state->pit_reload,savefailout);
+
+ for (i=0;i<3;i++) {
+ struct channel *c;
+ uint8_t pins;
+
+ if (i==0) {
+ c=&(pit_state->ch_0);
+ } else if (i==1) {
+ c=&(pit_state->ch_1);
+ } else {
+ c=&(pit_state->ch_2);
+ }
+
+ MAKE_KEY("ACCESS_MODE");
+ V3_CHKPT_SAVE(ctx, key, c->access_mode, savefailout);
+ MAKE_KEY("ACCESS_STATE");
+ V3_CHKPT_SAVE(ctx, key, c->access_state, savefailout);
+ MAKE_KEY("RUN_STATE");
+ V3_CHKPT_SAVE(ctx, key, c->run_state, savefailout);
+ MAKE_KEY("OP_MODE");
+ V3_CHKPT_SAVE(ctx, key, c->op_mode, savefailout);
+ MAKE_KEY("COUNTER");
+ V3_CHKPT_SAVE(ctx, key, c->counter, savefailout);
+ MAKE_KEY("RELOAD_VALUE");
+ V3_CHKPT_SAVE(ctx, key, c->reload_value, savefailout);
+ MAKE_KEY("LATCH_STATE");
+ V3_CHKPT_SAVE(ctx, key, c->latch_state, savefailout);
+ MAKE_KEY("READ_STATE");
+ V3_CHKPT_SAVE(ctx, key, c->read_state, savefailout);
+
+ pins = (c->output_pin) | (c->gate_input_pin << 1);
+ MAKE_KEY("PINS");
+ V3_CHKPT_SAVE(ctx, key, pins, savefailout);
+ }
+
+ V3_CHKPT_SAVE(ctx, "PIT_SPEAKER", pit_state->speaker,savefailout);
return 0;
static int pit_load(struct v3_chkpt_ctx * ctx, void * private_data) {
struct pit * pit_state = (struct pit *)private_data;
-
- V3_CHKPT_LOAD_AUTOTAG(ctx, pit_state->pit_counter,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, pit_state->pit_reload,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, pit_state->ch_0,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, pit_state->ch_1,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, pit_state->ch_2,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, pit_state->speaker,loadfailout);
+ int i;
+ char key[KEY_MAX];
+
+ V3_CHKPT_LOAD(ctx, "PIT_COUNTER", pit_state->pit_counter,loadfailout);
+ V3_CHKPT_LOAD(ctx, "PIT_RELOAD", pit_state->pit_reload,loadfailout);
+
+ for (i=0;i<3;i++) {
+ struct channel *c;
+ uint8_t pins;
+
+ if (i==0) {
+ c=&(pit_state->ch_0);
+ } else if (i==1) {
+ c=&(pit_state->ch_1);
+ } else {
+ c=&(pit_state->ch_2);
+ }
+
+ MAKE_KEY("ACCESS_MODE");
+ V3_CHKPT_LOAD(ctx, key, c->access_mode, loadfailout);
+ MAKE_KEY("ACCESS_STATE");
+ V3_CHKPT_LOAD(ctx, key, c->access_state, loadfailout);
+ MAKE_KEY("RUN_STATE");
+ V3_CHKPT_LOAD(ctx, key, c->run_state, loadfailout);
+ MAKE_KEY("OP_MODE");
+ V3_CHKPT_LOAD(ctx, key, c->op_mode, loadfailout);
+ MAKE_KEY("COUNTER");
+ V3_CHKPT_LOAD(ctx, key, c->counter, loadfailout);
+ MAKE_KEY("RELOAD_VALUE");
+ V3_CHKPT_LOAD(ctx, key, c->reload_value, loadfailout);
+ MAKE_KEY("LATCH_STATE");
+ V3_CHKPT_LOAD(ctx, key, c->latch_state, loadfailout);
+ MAKE_KEY("READ_STATE");
+ V3_CHKPT_LOAD(ctx, key, c->read_state, loadfailout);
+
+ pins = (c->output_pin) | (c->gate_input_pin << 1);
+ MAKE_KEY("PINS");
+ V3_CHKPT_LOAD(ctx, key, pins, loadfailout);
+ }
+
+ V3_CHKPT_LOAD(ctx, "PIT_SPEAKER", pit_state->speaker,loadfailout);
return 0;
}
#ifdef V3_CONFIG_CHECKPOINT
+
+#define KEY_MAX 128
+#define MAKE_KEY(x) snprintf(key,KEY_MAX,"%s%d",x,i);
+
static int apic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
struct apic_dev_state * apic_state = (struct apic_dev_state *)private_data;
int i = 0;
uint32_t temp;
+ char key[KEY_MAX];
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->num_apics,savefailout);
+ V3_CHKPT_SAVE(ctx, "NUM_APICS", apic_state->num_apics,savefailout);
- //V3_CHKPT_STD_SAVE(ctx,apic_state->state_lock);
for (i = 0; i < apic_state->num_apics; i++) {
-
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].base_addr,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].base_addr_msr,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].lapic_id,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].apic_ver,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].ext_apic_ctrl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].local_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].tmr_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].tmr_div_cfg,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].lint0_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].lint1_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].perf_ctr_loc_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].therm_loc_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].err_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].err_status,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].spurious_int,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].int_cmd,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].log_dst,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].dst_fmt,savefailout);
-
- // APR and PPR are stored only for compatability
- // TPR is in APIC_TPR, APR and PPR are derived
+ drain_irq_entries(&(apic_state->apics[i]));
+
+ MAKE_KEY("BASE_ADDR");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].base_addr,savefailout);
+ MAKE_KEY("BASE_ADDR_MSR");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].base_addr_msr,savefailout);
+ MAKE_KEY("LAPIC_ID");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].lapic_id,savefailout);
+ MAKE_KEY("APIC_VER");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].apic_ver,savefailout);
+ MAKE_KEY("EXT_APIC_CTRL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].ext_apic_ctrl,savefailout);
+ MAKE_KEY("LOCAL_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].local_vec_tbl,savefailout);
+ MAKE_KEY("TMR_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].tmr_vec_tbl,savefailout);
+ MAKE_KEY("TMR_DIV_CFG");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].tmr_div_cfg,savefailout);
+ MAKE_KEY("LINT0_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].lint0_vec_tbl,savefailout);
+ MAKE_KEY("LINT1_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].lint1_vec_tbl,savefailout);
+ MAKE_KEY("PERF_CTR_LOC_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].perf_ctr_loc_vec_tbl,savefailout);
+ MAKE_KEY("THERM_LOC_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].therm_loc_vec_tbl,savefailout);
+ MAKE_KEY("ERR_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].err_vec_tbl,savefailout);
+ MAKE_KEY("ERR_STATUS");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].err_status,savefailout);
+ MAKE_KEY("SPURIOUS_INT");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].spurious_int,savefailout);
+ MAKE_KEY("INT_CMD");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].int_cmd,savefailout);
+ MAKE_KEY("LOG_DST");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].log_dst,savefailout);
+ MAKE_KEY("DST_FMT");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].dst_fmt,savefailout);
+
+ // APR and PPR are stored only for compatability
+ // TPR is in APIC_TPR, APR and PPR are derived
- temp = get_apic_apr(&(apic_state->apics[i]));
- V3_CHKPT_SAVE_AUTOTAG(ctx, temp,savefailout);
- temp = get_apic_tpr(&(apic_state->apics[i]));
- V3_CHKPT_SAVE_AUTOTAG(ctx,temp,savefailout);
- temp = get_apic_ppr(&(apic_state->apics[i]));
- V3_CHKPT_SAVE_AUTOTAG(ctx, temp,savefailout);
-
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].ext_apic_feature,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].spec_eoi,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].tmr_cur_cnt,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].tmr_init_cnt,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].ext_intr_vec_tbl,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].rem_rd_data,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].ipi_state,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].int_req_reg,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].int_svc_reg,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].int_en_reg,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].trig_mode_reg,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, apic_state->apics[i].eoi,savefailout);
+ temp = get_apic_apr(&(apic_state->apics[i]));
+ MAKE_KEY("ARB_PRIO");
+ V3_CHKPT_SAVE(ctx, key, temp,savefailout);
+ temp = get_apic_tpr(&(apic_state->apics[i]));
+ MAKE_KEY("TASK_PRIO");
+ V3_CHKPT_SAVE(ctx,key,temp,savefailout);
+ temp = get_apic_ppr(&(apic_state->apics[i]));
+ MAKE_KEY("PROC_PRIO");
+ V3_CHKPT_SAVE(ctx, key,temp,savefailout);
+
+ MAKE_KEY("EXT_APIC_FEATURE");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].ext_apic_feature,savefailout);
+ MAKE_KEY("SPEC_EOI");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].spec_eoi,savefailout);
+ MAKE_KEY("TMR_CUR_CNT");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].tmr_cur_cnt,savefailout);
+
+ MAKE_KEY("TMR_INIT_CNT");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].tmr_init_cnt,savefailout);
+ MAKE_KEY("EXT_INTR_VEC_TBL");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].ext_intr_vec_tbl,savefailout);
+
+ MAKE_KEY("REM_RD_DATA");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].rem_rd_data,savefailout);
+ MAKE_KEY("IPI_STATE");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].ipi_state,savefailout);
+ MAKE_KEY("INT_REQ_REG");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].int_req_reg,savefailout);
+ MAKE_KEY("INT_SVC_REG");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].int_svc_reg,savefailout);
+ MAKE_KEY("INT_EN_REG");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].int_en_reg,savefailout);
+ MAKE_KEY("TRIG_MODE_REG");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].trig_mode_reg,savefailout);
+ MAKE_KEY("EOI");
+ V3_CHKPT_SAVE(ctx, key, apic_state->apics[i].eoi,savefailout);
}
struct apic_dev_state *apic_state = (struct apic_dev_state *)private_data;
int i = 0;
uint32_t temp;
+ char key[KEY_MAX];
- V3_CHKPT_LOAD_AUTOTAG(ctx,apic_state->num_apics, loadfailout);
+ V3_CHKPT_LOAD(ctx,"NUM_APICS", apic_state->num_apics, loadfailout);
for (i = 0; i < apic_state->num_apics; i++) {
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].base_addr, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].base_addr_msr, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].lapic_id, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].apic_ver, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].ext_apic_ctrl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].local_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].tmr_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].tmr_div_cfg, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].lint0_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].lint1_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].perf_ctr_loc_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].therm_loc_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].err_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].err_status, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].spurious_int, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].int_cmd, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].log_dst, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].dst_fmt, loadfailout);
-
- // APR is ignored
- V3_CHKPT_LOAD_AUTOTAG(ctx, temp, loadfailout);
- // TPR is written back to APIC_TPR
- V3_CHKPT_LOAD_AUTOTAG(ctx, temp, loadfailout);
- set_apic_tpr(&(apic_state->apics[i]),temp);
- // PPR is ignored
- V3_CHKPT_LOAD_AUTOTAG(ctx, temp, loadfailout);
-
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].ext_apic_feature, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].spec_eoi, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].tmr_cur_cnt, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].tmr_init_cnt, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].ext_intr_vec_tbl, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].rem_rd_data, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].ipi_state, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].int_req_reg, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].int_svc_reg, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].int_en_reg, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].trig_mode_reg, loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, apic_state->apics[i].eoi, loadfailout);
+ drain_irq_entries(&(apic_state->apics[i]));
+
+ MAKE_KEY("BASE_ADDR");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].base_addr,loadfailout);
+ MAKE_KEY("BASE_ADDR_MSR");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].base_addr_msr,loadfailout);
+ MAKE_KEY("LAPIC_ID");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].lapic_id,loadfailout);
+ MAKE_KEY("APIC_VER");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].apic_ver,loadfailout);
+ MAKE_KEY("EXT_APIC_CTRL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].ext_apic_ctrl,loadfailout);
+ MAKE_KEY("LOCAL_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].local_vec_tbl,loadfailout);
+ MAKE_KEY("TMR_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].tmr_vec_tbl,loadfailout);
+ MAKE_KEY("TMR_DIV_CFG");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].tmr_div_cfg,loadfailout);
+ MAKE_KEY("LINT0_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].lint0_vec_tbl,loadfailout);
+ MAKE_KEY("LINT1_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].lint1_vec_tbl,loadfailout);
+ MAKE_KEY("PERF_CTR_LOC_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].perf_ctr_loc_vec_tbl,loadfailout);
+ MAKE_KEY("THERM_LOC_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].therm_loc_vec_tbl,loadfailout);
+ MAKE_KEY("ERR_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].err_vec_tbl,loadfailout);
+ MAKE_KEY("ERR_STATUS");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].err_status,loadfailout);
+ MAKE_KEY("SPURIOUS_INT");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].spurious_int,loadfailout);
+ MAKE_KEY("INT_CMD");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].int_cmd,loadfailout);
+ MAKE_KEY("LOG_DST");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].log_dst,loadfailout);
+ MAKE_KEY("DST_FMT");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].dst_fmt,loadfailout);
+
+ // APR and PPR are stored only for compatability
+ // TPR is in APIC_TPR, APR and PPR are derived
+
+ MAKE_KEY("ARB_PRIO");
+ V3_CHKPT_LOAD(ctx, key, temp,loadfailout);
+ // discarded
+
+ MAKE_KEY("TASK_PRIO");
+ V3_CHKPT_LOAD(ctx,key,temp,loadfailout);
+ set_apic_tpr(&(apic_state->apics[i]),temp);
+
+ MAKE_KEY("PROC_PRIO");
+ V3_CHKPT_LOAD(ctx, key,temp,loadfailout);
+ // discarded
+
+
+ MAKE_KEY("EXT_APIC_FEATURE");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].ext_apic_feature,loadfailout);
+ MAKE_KEY("SPEC_EOI");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].spec_eoi,loadfailout);
+ MAKE_KEY("TMR_CUR_CNT");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].tmr_cur_cnt,loadfailout);
+
+ MAKE_KEY("TMR_INIT_CNT");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].tmr_init_cnt,loadfailout);
+ MAKE_KEY("EXT_INTR_VEC_TBL");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].ext_intr_vec_tbl,loadfailout);
+
+ MAKE_KEY("REM_RD_DATA");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].rem_rd_data,loadfailout);
+ MAKE_KEY("IPI_STATE");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].ipi_state,loadfailout);
+ MAKE_KEY("INT_REQ_REG");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].int_req_reg,loadfailout);
+ MAKE_KEY("INT_SVC_REG");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].int_svc_reg,loadfailout);
+ MAKE_KEY("INT_EN_REG");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].int_en_reg,loadfailout);
+ MAKE_KEY("TRIG_MODE_REG");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].trig_mode_reg,loadfailout);
+ MAKE_KEY("EOI");
+ V3_CHKPT_LOAD(ctx, key, apic_state->apics[i].eoi,loadfailout);
}
-
-
+
+
return 0;
-
+
loadfailout:
PrintError("Failed to load apic\n");
return -1;
-
+
}
#endif
static int io_apic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
struct io_apic_state * io_apic = (struct io_apic_state *)private_data;
- V3_CHKPT_SAVE_AUTOTAG(ctx, io_apic->base_addr,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, io_apic->index_reg,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, io_apic->ioapic_id,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, io_apic->ioapic_ver,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, io_apic->ioapic_arb_id,savefailout);
- V3_CHKPT_SAVE_AUTOTAG(ctx, io_apic->redir_tbl,savefailout);
+
+ V3_CHKPT_SAVE(ctx, "BASE_ADDR" ,io_apic->base_addr,savefailout);
+ V3_CHKPT_SAVE(ctx, "INDEX_REG", io_apic->index_reg,savefailout);
+ V3_CHKPT_SAVE(ctx, "IOAPIC_ID", io_apic->ioapic_id,savefailout);
+ V3_CHKPT_SAVE(ctx, "IOAPIC_VER", io_apic->ioapic_ver,savefailout);
+ V3_CHKPT_SAVE(ctx, "IOAPIC_ARB_ID", io_apic->ioapic_arb_id,savefailout);
+ V3_CHKPT_SAVE(ctx, "REDIR_TABLE", io_apic->redir_tbl,savefailout);
return 0;
static int io_apic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
struct io_apic_state * io_apic = (struct io_apic_state *)private_data;
- V3_CHKPT_LOAD_AUTOTAG(ctx, io_apic->base_addr,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, io_apic->index_reg,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, io_apic->ioapic_id,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, io_apic->ioapic_ver,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, io_apic->ioapic_arb_id,loadfailout);
- V3_CHKPT_LOAD_AUTOTAG(ctx, io_apic->redir_tbl,loadfailout);
+ V3_CHKPT_LOAD(ctx, "BASE_ADDR", io_apic->base_addr,loadfailout);
+ V3_CHKPT_LOAD(ctx, "INDEX_REG", io_apic->index_reg,loadfailout);
+ V3_CHKPT_LOAD(ctx, "IOAPIC_ID", io_apic->ioapic_id,loadfailout);
+ V3_CHKPT_LOAD(ctx, "IOAPIC_VER", io_apic->ioapic_ver,loadfailout);
+ V3_CHKPT_LOAD(ctx, "IOAPIC_ARB_ID", io_apic->ioapic_arb_id,loadfailout);
+ V3_CHKPT_LOAD(ctx, "REDIR_TABLE", io_apic->redir_tbl,loadfailout);
return 0;
#ifdef V3_CONFIG_CHECKPOINT
int v3_svm_save_core(struct guest_info * core, void * ctx){
- if (V3_CHKPT_SAVE(ctx, "cpl", core->cpl)) {
- PrintError("Could not save SVM cpl\n");
- return -1;
- }
-
- if (v3_chkpt_save(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data)) {
+ vmcb_saved_state_t * guest_area = GET_VMCB_SAVE_STATE_AREA(core->vmm_data);
+
+ // Special case saves of data we need immediate access to
+ // in some cases
+ V3_CHKPT_SAVE(ctx, "CPL", core->cpl, failout);
+ V3_CHKPT_SAVE(ctx,"STAR", guest_area->star, failout);
+ V3_CHKPT_SAVE(ctx,"CSTAR", guest_area->cstar, failout);
+ V3_CHKPT_SAVE(ctx,"LSTAR", guest_area->lstar, failout);
+ V3_CHKPT_SAVE(ctx,"SFMASK", guest_area->sfmask, failout);
+ V3_CHKPT_SAVE(ctx,"KERNELGSBASE", guest_area->KernelGsBase, failout);
+ V3_CHKPT_SAVE(ctx,"SYSENTER_CS", guest_area->sysenter_cs, failout);
+ V3_CHKPT_SAVE(ctx,"SYSENTER_ESP", guest_area->sysenter_esp, failout);
+ V3_CHKPT_SAVE(ctx,"SYSENTER_EIP", guest_area->sysenter_eip, failout);
+
+// and then we save the whole enchilada
+ if (v3_chkpt_save(ctx, "VMCB_DATA", PAGE_SIZE, core->vmm_data)) {
PrintError("Could not save SVM vmcb\n");
- return -1;
+ goto failout;
}
return 0;
+
+ failout:
+ PrintError("Failed to save SVM state for core\n");
+ return -1;
+
}
int v3_svm_load_core(struct guest_info * core, void * ctx){
- if (V3_CHKPT_LOAD(ctx, "cpl", core->cpl)) {
- PrintError("Could not load SVM cpl\n");
- return -1;
- }
- if (v3_chkpt_load(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data) == -1) {
- return -1;
+ vmcb_saved_state_t * guest_area = GET_VMCB_SAVE_STATE_AREA(core->vmm_data);
+
+ // Reload what we special cased, which we will overwrite in a minute
+ V3_CHKPT_LOAD(ctx, "CPL", core->cpl, failout);
+ V3_CHKPT_LOAD(ctx,"STAR", guest_area->star, failout);
+ V3_CHKPT_LOAD(ctx,"CSTAR", guest_area->cstar, failout);
+ V3_CHKPT_LOAD(ctx,"LSTAR", guest_area->lstar, failout);
+ V3_CHKPT_LOAD(ctx,"SFMASK", guest_area->sfmask, failout);
+ V3_CHKPT_LOAD(ctx,"KERNELGSBASE", guest_area->KernelGsBase, failout);
+ V3_CHKPT_LOAD(ctx,"SYSENTER_CS", guest_area->sysenter_cs, failout);
+ V3_CHKPT_LOAD(ctx,"SYSENTER_ESP", guest_area->sysenter_esp, failout);
+ V3_CHKPT_LOAD(ctx,"SYSENTER_EIP", guest_area->sysenter_eip, failout);
+
+ // and then we load the whole enchilada
+ if (v3_chkpt_load(ctx, "VMCB_DATA", PAGE_SIZE, core->vmm_data)) {
+ PrintError("Could not load SVM vmcb\n");
+ goto failout;
}
return 0;
+
+ failout:
+ PrintError("Failed to save SVM state for core\n");
+ return -1;
+
}
#endif
extern v3_cpu_arch_t v3_mach_type;
void * ctx = NULL;
char key_name[16];
+ v3_reg_t tempreg;
+
+ PrintDebug("Loading core\n");
memset(key_name, 0, 16);
if (!ctx) {
PrintError("Could not open context to load core\n");
- return -1;
+ goto loadfailout;
}
V3_CHKPT_LOAD(ctx, "RIP", info->rip, loadfailout);
- V3_CHKPT_LOAD(ctx, "GPRS", info->vm_regs, loadfailout);
-
+
+ // GPRs
+ V3_CHKPT_LOAD(ctx,"RDI",info->vm_regs.rdi, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RSI",info->vm_regs.rsi, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RBP",info->vm_regs.rbp, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RSP",info->vm_regs.rsp, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RBX",info->vm_regs.rbx, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RDX",info->vm_regs.rdx, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RCX",info->vm_regs.rcx, loadfailout);
+ V3_CHKPT_LOAD(ctx,"RAX",info->vm_regs.rax, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R8",info->vm_regs.r8, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R9",info->vm_regs.r9, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R10",info->vm_regs.r10, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R11",info->vm_regs.r11, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R12",info->vm_regs.r12, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R13",info->vm_regs.r13, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R14",info->vm_regs.r14, loadfailout);
+ V3_CHKPT_LOAD(ctx,"R15",info->vm_regs.r15, loadfailout);
+
+ // Control registers
V3_CHKPT_LOAD(ctx, "CR0", info->ctrl_regs.cr0, loadfailout);
+ // there is no CR1
V3_CHKPT_LOAD(ctx, "CR2", info->ctrl_regs.cr2, loadfailout);
+ V3_CHKPT_LOAD(ctx, "CR3", info->ctrl_regs.cr3, loadfailout);
V3_CHKPT_LOAD(ctx, "CR4", info->ctrl_regs.cr4, loadfailout);
+ // There are no CR5,6,7
+ // CR8 is derived from apic_tpr
+ tempreg = (info->ctrl_regs.apic_tpr >> 4) & 0xf;
+ V3_CHKPT_LOAD(ctx, "CR8", tempreg, loadfailout);
V3_CHKPT_LOAD(ctx, "APIC_TPR", info->ctrl_regs.apic_tpr, loadfailout);
V3_CHKPT_LOAD(ctx, "RFLAGS", info->ctrl_regs.rflags, loadfailout);
V3_CHKPT_LOAD(ctx, "EFER", info->ctrl_regs.efer, loadfailout);
- V3_CHKPT_LOAD(ctx, "DBRS", info->dbg_regs, loadfailout);
- V3_CHKPT_LOAD(ctx, "SEGS", info->segments, loadfailout);
+ // Debug registers
+ V3_CHKPT_LOAD(ctx, "DR0", info->dbg_regs.dr0, loadfailout);
+ V3_CHKPT_LOAD(ctx, "DR1", info->dbg_regs.dr1, loadfailout);
+ V3_CHKPT_LOAD(ctx, "DR2", info->dbg_regs.dr2, loadfailout);
+ V3_CHKPT_LOAD(ctx, "DR3", info->dbg_regs.dr3, loadfailout);
+ // there is no DR4 or DR5
+ V3_CHKPT_LOAD(ctx, "DR6", info->dbg_regs.dr6, loadfailout);
+ V3_CHKPT_LOAD(ctx, "DR7", info->dbg_regs.dr7, loadfailout);
+
+ // Segment registers
+ V3_CHKPT_LOAD(ctx, "CS", info->segments.cs, loadfailout);
+ V3_CHKPT_LOAD(ctx, "DS", info->segments.ds, loadfailout);
+ V3_CHKPT_LOAD(ctx, "ES", info->segments.es, loadfailout);
+ V3_CHKPT_LOAD(ctx, "FS", info->segments.fs, loadfailout);
+ V3_CHKPT_LOAD(ctx, "GS", info->segments.gs, loadfailout);
+ V3_CHKPT_LOAD(ctx, "SS", info->segments.ss, loadfailout);
+ V3_CHKPT_LOAD(ctx, "LDTR", info->segments.ldtr, loadfailout);
+ V3_CHKPT_LOAD(ctx, "GDTR", info->segments.gdtr, loadfailout);
+ V3_CHKPT_LOAD(ctx, "IDTR", info->segments.idtr, loadfailout);
+ V3_CHKPT_LOAD(ctx, "TR", info->segments.tr, loadfailout);
+
+ // several MSRs...
+ V3_CHKPT_LOAD(ctx, "STAR", info->msrs.star, loadfailout);
+ V3_CHKPT_LOAD(ctx, "LSTAR", info->msrs.lstar, loadfailout);
+ V3_CHKPT_LOAD(ctx, "SFMASK", info->msrs.sfmask, loadfailout);
+ V3_CHKPT_LOAD(ctx, "KERN_GS_BASE", info->msrs.kern_gs_base, loadfailout);
+
+ // Some components of guest state captured in the shadow pager
V3_CHKPT_LOAD(ctx, "GUEST_CR3", info->shdw_pg_state.guest_cr3, loadfailout);
V3_CHKPT_LOAD(ctx, "GUEST_CRO", info->shdw_pg_state.guest_cr0, loadfailout);
V3_CHKPT_LOAD(ctx, "GUEST_EFER", info->shdw_pg_state.guest_efer, loadfailout);
- v3_chkpt_close_ctx(ctx);
+ v3_chkpt_close_ctx(ctx); ctx=0;
PrintDebug("Finished reading guest_info information\n");
if (v3_get_vm_mem_mode(info) == VIRTUAL_MEM) {
if (v3_activate_shadow_pt(info) == -1) {
PrintError("Failed to activate shadow page tables\n");
- return -1;
+ goto loadfailout;
}
} else {
if (v3_activate_passthrough_pt(info) == -1) {
PrintError("Failed to activate passthrough page tables\n");
- return -1;
+ goto loadfailout;
}
}
}
if (!ctx) {
PrintError("Could not open context to load SVM core\n");
- return -1;
+ goto loadfailout;
}
if (v3_svm_load_core(info, ctx) < 0 ) {
goto loadfailout;
}
- v3_chkpt_close_ctx(ctx);
+ v3_chkpt_close_ctx(ctx); ctx=0;
break;
}
if (!ctx) {
PrintError("Could not open context to load VMX core\n");
- return -1;
+ goto loadfailout;
}
if (v3_vmx_load_core(info, ctx) < 0) {
goto loadfailout;
}
- v3_chkpt_close_ctx(ctx);
+ v3_chkpt_close_ctx(ctx); ctx=0;
break;
}
default:
PrintError("Invalid CPU Type (%d)\n", v3_mach_type);
- return -1;
+ goto loadfailout;
}
PrintDebug("Load of core succeeded\n");
return 0;
loadfailout:
- PrintError("Failed to load core due to bad context load\n");
- v3_chkpt_close_ctx(ctx);
+ PrintError("Failed to load core\n");
+ if (ctx) { v3_chkpt_close_ctx(ctx);}
return -1;
}
+// GEM5 - Hypercall for initiating transfer to gem5 (checkpoint)
static int save_core(struct guest_info * info, struct v3_chkpt * chkpt) {
extern v3_cpu_arch_t v3_mach_type;
void * ctx = NULL;
char key_name[16];
+ v3_reg_t tempreg;
PrintDebug("Saving core\n");
memset(key_name, 0, 16);
-
snprintf(key_name, 16, "guest_info%d", info->vcpu_id);
ctx = v3_chkpt_open_ctx(chkpt, key_name);
if (!ctx) {
PrintError("Unable to open context to save core\n");
- return -1;
+ goto savefailout;
}
V3_CHKPT_SAVE(ctx, "RIP", info->rip, savefailout);
- V3_CHKPT_SAVE(ctx, "GPRS", info->vm_regs, savefailout);
-
+
+ // GPRs
+ V3_CHKPT_SAVE(ctx,"RDI",info->vm_regs.rdi, savefailout);
+ V3_CHKPT_SAVE(ctx,"RSI",info->vm_regs.rsi, savefailout);
+ V3_CHKPT_SAVE(ctx,"RBP",info->vm_regs.rbp, savefailout);
+ V3_CHKPT_SAVE(ctx,"RSP",info->vm_regs.rsp, savefailout);
+ V3_CHKPT_SAVE(ctx,"RBX",info->vm_regs.rbx, savefailout);
+ V3_CHKPT_SAVE(ctx,"RDX",info->vm_regs.rdx, savefailout);
+ V3_CHKPT_SAVE(ctx,"RCX",info->vm_regs.rcx, savefailout);
+ V3_CHKPT_SAVE(ctx,"RAX",info->vm_regs.rax, savefailout);
+ V3_CHKPT_SAVE(ctx,"R8",info->vm_regs.r8, savefailout);
+ V3_CHKPT_SAVE(ctx,"R9",info->vm_regs.r9, savefailout);
+ V3_CHKPT_SAVE(ctx,"R10",info->vm_regs.r10, savefailout);
+ V3_CHKPT_SAVE(ctx,"R11",info->vm_regs.r11, savefailout);
+ V3_CHKPT_SAVE(ctx,"R12",info->vm_regs.r12, savefailout);
+ V3_CHKPT_SAVE(ctx,"R13",info->vm_regs.r13, savefailout);
+ V3_CHKPT_SAVE(ctx,"R14",info->vm_regs.r14, savefailout);
+ V3_CHKPT_SAVE(ctx,"R15",info->vm_regs.r15, savefailout);
+
+ // Control registers
V3_CHKPT_SAVE(ctx, "CR0", info->ctrl_regs.cr0, savefailout);
+ // there is no CR1
V3_CHKPT_SAVE(ctx, "CR2", info->ctrl_regs.cr2, savefailout);
+ V3_CHKPT_SAVE(ctx, "CR3", info->ctrl_regs.cr3, savefailout);
V3_CHKPT_SAVE(ctx, "CR4", info->ctrl_regs.cr4, savefailout);
+ // There are no CR5,6,7
+ // CR8 is derived from apic_tpr
+ tempreg = (info->ctrl_regs.apic_tpr >> 4) & 0xf;
+ V3_CHKPT_SAVE(ctx, "CR8", tempreg, savefailout);
V3_CHKPT_SAVE(ctx, "APIC_TPR", info->ctrl_regs.apic_tpr, savefailout);
V3_CHKPT_SAVE(ctx, "RFLAGS", info->ctrl_regs.rflags, savefailout);
V3_CHKPT_SAVE(ctx, "EFER", info->ctrl_regs.efer, savefailout);
- V3_CHKPT_SAVE(ctx, "DBRS", info->dbg_regs, savefailout);
- V3_CHKPT_SAVE(ctx, "SEGS", info->segments, savefailout);
+ // Debug registers
+ V3_CHKPT_SAVE(ctx, "DR0", info->dbg_regs.dr0, savefailout);
+ V3_CHKPT_SAVE(ctx, "DR1", info->dbg_regs.dr1, savefailout);
+ V3_CHKPT_SAVE(ctx, "DR2", info->dbg_regs.dr2, savefailout);
+ V3_CHKPT_SAVE(ctx, "DR3", info->dbg_regs.dr3, savefailout);
+ // there is no DR4 or DR5
+ V3_CHKPT_SAVE(ctx, "DR6", info->dbg_regs.dr6, savefailout);
+ V3_CHKPT_SAVE(ctx, "DR7", info->dbg_regs.dr7, savefailout);
+
+ // Segment registers
+ V3_CHKPT_SAVE(ctx, "CS", info->segments.cs, savefailout);
+ V3_CHKPT_SAVE(ctx, "DS", info->segments.ds, savefailout);
+ V3_CHKPT_SAVE(ctx, "ES", info->segments.es, savefailout);
+ V3_CHKPT_SAVE(ctx, "FS", info->segments.fs, savefailout);
+ V3_CHKPT_SAVE(ctx, "GS", info->segments.gs, savefailout);
+ V3_CHKPT_SAVE(ctx, "SS", info->segments.ss, savefailout);
+ V3_CHKPT_SAVE(ctx, "LDTR", info->segments.ldtr, savefailout);
+ V3_CHKPT_SAVE(ctx, "GDTR", info->segments.gdtr, savefailout);
+ V3_CHKPT_SAVE(ctx, "IDTR", info->segments.idtr, savefailout);
+ V3_CHKPT_SAVE(ctx, "TR", info->segments.tr, savefailout);
+
+ // several MSRs...
+ V3_CHKPT_SAVE(ctx, "STAR", info->msrs.star, savefailout);
+ V3_CHKPT_SAVE(ctx, "LSTAR", info->msrs.lstar, savefailout);
+ V3_CHKPT_SAVE(ctx, "SFMASK", info->msrs.sfmask, savefailout);
+ V3_CHKPT_SAVE(ctx, "KERN_GS_BASE", info->msrs.kern_gs_base, savefailout);
+
+ // Some components of guest state captured in the shadow pager
V3_CHKPT_SAVE(ctx, "GUEST_CR3", info->shdw_pg_state.guest_cr3, savefailout);
V3_CHKPT_SAVE(ctx, "GUEST_CRO", info->shdw_pg_state.guest_cr0, savefailout);
V3_CHKPT_SAVE(ctx, "GUEST_EFER", info->shdw_pg_state.guest_efer, savefailout);
- v3_chkpt_close_ctx(ctx);
+ v3_chkpt_close_ctx(ctx); ctx=0;
//Architechture specific code
switch (v3_mach_type) {
if (!ctx) {
PrintError("Could not open context to store SVM core\n");
- return -1;
+ goto savefailout;
}
if (v3_svm_save_core(info, ctx) < 0) {
goto savefailout;
}
- v3_chkpt_close_ctx(ctx);
+ v3_chkpt_close_ctx(ctx); ctx=0;;
break;
}
case V3_VMX_CPU:
if (!ctx) {
PrintError("Could not open context to store VMX core\n");
- return -1;
+ goto savefailout;
}
if (v3_vmx_save_core(info, ctx) == -1) {
goto savefailout;
}
- v3_chkpt_close_ctx(ctx);
+ v3_chkpt_close_ctx(ctx); ctx=0;
break;
}
default:
PrintError("Invalid CPU Type (%d)\n", v3_mach_type);
- return -1;
+ goto savefailout;
}
return 0;
savefailout:
- PrintError("Failed to save core due to bad context save\n");
- v3_chkpt_close_ctx(ctx);
+ PrintError("Failed to save core\n");
+ if (ctx) { v3_chkpt_close_ctx(ctx); }
return -1;
}
+//
+// GEM5 - Madhav has debug code here for printing instrucions
+//
int v3_chkpt_save_vm(struct v3_vm_info * vm, char * store, char * url) {
struct v3_chkpt * chkpt = NULL;
