state->master_isr &= ~(0x01 << i);
break;
}
- }
+ }
PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
} else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) {
PrintDebug("8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level);
return -1;
}
+ if (cw2->EOI) {
+ if (pic_get_intr_number(core, state) != -1) {
+ PrintError("Interrupt pending after EOI\n");
+ }
+ }
+
+
state->master_ocw2 = cw;
} else if (IS_OCW3(cw)) {
PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
return -1;
}
+ if (cw2->EOI) {
+ if (pic_get_intr_number(core, state) != -1) {
+ PrintError("Interrupt pending after EOI\n");
+ }
+ }
+
+
+
state->slave_ocw2 = cw;
} else if (IS_OCW3(cw)) {
// Basically sets the IRR/ISR read flag