struct {
int num_ports;
uint16_t default_base_port;
- int (*io_read)(ushort_t port, void * dst, uint_t length, struct vm_device * dev);
- int (*io_write)(ushort_t port, void * src, uint_t length, struct vm_device * dev);
+ int (*io_read)(ushort_t port, void * dst, uint_t length, void * private_data);
+ int (*io_write)(ushort_t port, void * src, uint_t length, void * private_data);
};
};
+
+ void * private_data;
// Internal PCI data
uint32_t val;
};
-#define PCI_IO_BASE(bar_val) (bar_val & 0xfffffffc)
-#define PCI_MEM32_BASE(bar_val) (bar_val & 0xfffffff0)
+#define PCI_IO_MASK 0xfffffffc
+#define PCI_MEM32_MASK 0xfffffff0
+
+#define PCI_IO_BASE(bar_val) (bar_val & PCI_IO_MASK)
+#define PCI_MEM32_BASE(bar_val) (bar_val & PCI_MEM32_MASK)
struct pci_device {
#define DMA_CHANNEL_FLAG 0x08
-static int write_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
+static int write_dma_port(ushort_t port, void * src, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
}
-static int read_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
+static int read_dma_port(ushort_t port, void * dst, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
bars[4].io_read = read_dma_port;
bars[4].io_write = write_dma_port;
-
+ bars[4].private_data = dev;
+
pci_dev = v3_pci_register_device(ide->pci_bus, PCI_STD_DEVICE, 0, sb_pci->dev_num, 1,
"PIIX3_IDE", bars,
pci_config_update, NULL, NULL, dev);
return 0;
}
-static int virtio_io_write(uint16_t port, void * src, uint_t length, struct vm_device * dev) {
+static int virtio_io_write(uint16_t port, void * src, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct virtio_balloon_state * virtio = (struct virtio_balloon_state *)dev->private_data;
int port_idx = port % virtio->io_range_size;
}
-static int virtio_io_read(uint16_t port, void * dst, uint_t length, struct vm_device * dev) {
+static int virtio_io_read(uint16_t port, void * dst, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct virtio_balloon_state * virtio = (struct virtio_balloon_state *)dev->private_data;
int port_idx = port % virtio->io_range_size;
bars[0].io_read = virtio_io_read;
bars[0].io_write = virtio_io_write;
+ bars[0].private_data = dev;
+
pci_dev = v3_pci_register_device(pci_bus, PCI_STD_DEVICE,
0, PCI_AUTO_DEV_NUM, 0,
return 0;
}
-static int virtio_io_write(uint16_t port, void * src, uint_t length, struct vm_device * dev) {
+static int virtio_io_write(uint16_t port, void * src, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct virtio_blk_state * virtio = (struct virtio_blk_state *)dev->private_data;
int port_idx = port % virtio->io_range_size;
}
-static int virtio_io_read(uint16_t port, void * dst, uint_t length, struct vm_device * dev) {
+static int virtio_io_read(uint16_t port, void * dst, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct virtio_blk_state * virtio = (struct virtio_blk_state *)dev->private_data;
int port_idx = port % virtio->io_range_size;
bars[0].io_read = virtio_io_read;
bars[0].io_write = virtio_io_write;
+ bars[0].private_data = dev;
pci_dev = v3_pci_register_device(pci_bus, PCI_STD_DEVICE,
0, PCI_AUTO_DEV_NUM, 0,
}
-static int virtio_io_write(uint16_t port, void * src, uint_t length, struct vm_device * dev) {
+static int virtio_io_write(uint16_t port, void * src, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct virtio_sym_state * virtio = (struct virtio_sym_state *)dev->private_data;
int port_idx = port % virtio->io_range_size;
}
-static int virtio_io_read(uint16_t port, void * dst, uint_t length, struct vm_device * dev) {
+static int virtio_io_read(uint16_t port, void * dst, uint_t length, void * private_data) {
+ struct vm_device * dev = (struct vm_device *)private_data;
struct virtio_sym_state * virtio = (struct virtio_sym_state *)dev->private_data;
int port_idx = port % virtio->io_range_size;
bars[0].io_read = virtio_io_read;
bars[0].io_write = virtio_io_write;
+ bars[0].private_data = dev;
pci_dev = v3_pci_register_device(pci_bus, PCI_STD_DEVICE,
0, PCI_AUTO_DEV_NUM, 0,
PrintDebug("Rehooking PCI IO port (old port=%u) (new port=%u)\n",
PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
- v3_dev_unhook_io(pci->vm_dev, PCI_IO_BASE(bar->val) + i);
+ v3_unhook_io_port(pci->vm_dev->vm, PCI_IO_BASE(bar->val) + i);
- if (v3_dev_hook_io(pci->vm_dev, PCI_IO_BASE(new_val) + i,
- bar->io_read, bar->io_write) == -1) {
+ if (v3_hook_io_port(pci->vm_dev->vm, PCI_IO_BASE(new_val) + i,
+ bar->io_read, bar->io_write,
+ bar->private_data) == -1) {
PrintError("Could not hook PCI IO port (old port=%u) (new port=%u)\n",
PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
// hook IO
if (pci_dev->bar[i].default_base_port != 0xffff) {
- if (v3_dev_hook_io(pci_dev->vm_dev, pci_dev->bar[i].default_base_port + j,
- pci_dev->bar[i].io_read, pci_dev->bar[i].io_write) == -1) {
+ if (v3_hook_io_port(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_port + j,
+ pci_dev->bar[i].io_read, pci_dev->bar[i].io_write,
+ pci_dev->bar[i].private_data) == -1) {
PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
return -1;
}
//copy bars
for (i = 0; i < 6; i ++) {
pci_dev->bar[i].type = bars[i].type;
+ pci_dev->bar[i].private_data = bars[i].private_data;
if (pci_dev->bar[i].type == PCI_BAR_IO) {
pci_dev->bar[i].num_ports = bars[i].num_ports;