};
+void v3_clear_pending_intr(struct guest_info * core);
void v3_register_intr_controller(struct guest_info * info, struct intr_ctrl_ops * ops, void * state);
return -1;
}
+ v3_clear_pending_intr(dev->vm);
+
if (IS_ICW1(cw)) {
PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
return -1;
}
+ v3_clear_pending_intr(dev->vm);
+
if (state->master_state == ICW2) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
state->master_icw2 = cw;
+
+
if (cw1->sngl == 0) {
state->master_state = ICW3;
} else if (cw1->ic4 == 1) {
state->master_state = READY;
}
+
+
} else if (state->master_state == ICW3) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
return -1;
}
+ v3_clear_pending_intr(dev->vm);
+
if (IS_ICW1(cw)) {
PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
state->slave_icw1 = cw;
return -1;
}
+ v3_clear_pending_intr(dev->vm);
+
+
if (state->slave_state == ICW2) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
// Interrupt was taken fully vectored
info->intr_state.irq_started = 0;
- } else {
+ } else if ((info->intr_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 1)) {
#ifdef CONFIG_DEBUG_INTERRUPTS
PrintDebug("EXIT INT INFO is set (vec=%d)\n", guest_ctrl->exit_int_info.vector);
#endif
static int update_irq_entry_state(struct guest_info * info) {
vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
+
+ if (info->intr_state.irq_pending == 0) {
+ guest_ctrl->guest_ctrl.V_IRQ = 0;
+ guest_ctrl->guest_ctrl.V_INTR_VECTOR = 0;
+ }
+
if (v3_excp_pending(info)) {
uint_t excp = v3_get_excp_number(info);
}
+void v3_clear_pending_intr(struct guest_info * core) {
+ struct v3_intr_state * intr_state = &(core->intr_state);
+
+ intr_state->irq_pending = 0;
+
+}
+
v3_intr_type_t v3_intr_pending(struct guest_info * info) {
struct v3_intr_state * intr_state = &(info->intr_state);