vmx updates

diff --git a/palacios/include/palacios/vmx.h b/palacios/include/palacios/vmx.h
index 7a0a039..2fae017 100644 (file)
--- a/palacios/include/palacios/vmx.h
+++ b/palacios/include/palacios/vmx.h
@@ -213,6 +213,8 @@ struct vmx_data {
     struct vmx_sec_proc_ctrls sec_proc_ctrls;
     struct vmx_exit_ctrls exit_ctrls;
     struct vmx_entry_ctrls entry_ctrls;
+
+    struct vmx_exception_bitmap excp_bmap;
 };
 
 int v3_is_vmx_capable();

diff --git a/palacios/include/palacios/vmx_hw_info.h b/palacios/include/palacios/vmx_hw_info.h
index e130545..726d994 100644 (file)
--- a/palacios/include/palacios/vmx_hw_info.h
+++ b/palacios/include/palacios/vmx_hw_info.h
@@ -152,7 +152,7 @@ struct vmx_hw_info {
     struct vmx_ctrl_field proc_ctrls;
     struct vmx_ctrl_field exit_ctrls;
     struct vmx_ctrl_field entry_ctrls;
-    struct vmx_ctrl_field proc_ctrls_2;
+    struct vmx_ctrl_field sec_proc_ctrls;
 
     struct vmx_cr_field cr0;
     struct vmx_cr_field cr4;

diff --git a/palacios/src/palacios/vmcs.c b/palacios/src/palacios/vmcs.c
index c355cae..04b8bf9 100644 (file)
--- a/palacios/src/palacios/vmcs.c
+++ b/palacios/src/palacios/vmcs.c
@@ -202,6 +202,7 @@ int v3_update_vmcs_ctrl_fields(struct guest_info * info) {
 
     vmx_ret |= check_vmcs_write(VMCS_EXIT_CTRLS, arch_data->exit_ctrls.value);
     vmx_ret |= check_vmcs_write(VMCS_ENTRY_CTRLS, arch_data->entry_ctrls.value);
+    vmx_ret |= check_vmcs_write(VMCS_EXCP_BITMAP, arch_data->excp_bmap.value);
 
     return vmx_ret;
 }

diff --git a/palacios/src/palacios/vmx.c b/palacios/src/palacios/vmx.c
index 4326788..24b0089 100644 (file)
--- a/palacios/src/palacios/vmx.c
+++ b/palacios/src/palacios/vmx.c
@@ -99,7 +99,6 @@ static addr_t allocate_vmcs() {
 
 static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state) {
     int vmx_ret = 0;
-    struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
 
     // disable global interrupts for vm state initialization
     v3_disable_ints();
@@ -115,6 +114,18 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
     }
 
 
+    /*** Setup default state from HW ***/
+
+    vmx_state->pin_ctrls.value = hw_info.pin_ctrls.def_val;
+    vmx_state->pri_proc_ctrls.value = hw_info.proc_ctrls.def_val;
+    vmx_state->exit_ctrls.value = hw_info.exit_ctrls.def_val;
+    vmx_state->entry_ctrls.value = hw_info.entry_ctrls.def_val;;
+
+    /* Print Control MSRs */
+    PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)hw_info.cr0.value);
+    PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)hw_info.cr4.value);
+
+
 
     /******* Setup Host State **********/
 
@@ -170,21 +181,12 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
   
 
     /********** Setup and VMX Control Fields from MSR ***********/
-    /* Setup IO map */
-
 
-    struct v3_msr tmp_msr;
-
-    v3_get_msr(VMX_PINBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
 
     /* Add external interrupts, NMI exiting, and virtual NMI */
-    vmx_state->pin_ctrls.value =  tmp_msr.lo;
     vmx_state->pin_ctrls.nmi_exit = 1;
     vmx_state->pin_ctrls.ext_int_exit = 1;
 
-    v3_get_msr(VMX_PROCBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
-
-    vmx_state->pri_proc_ctrls.value = tmp_msr.lo;
     vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
     vmx_state->pri_proc_ctrls.hlt_exit = 1;
     vmx_state->pri_proc_ctrls.invlpg_exit = 1;
@@ -195,6 +197,7 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
     vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
 #endif
 
+    /* Setup IO map */
     vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->vm_info->io_map.arch_data));
     vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR, 
             (addr_t)V3_PAddr(info->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
@@ -202,40 +205,19 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
 
     vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->vm_info->msr_map.arch_data));
 
-    v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
-    vmx_state->exit_ctrls.value = tmp_msr.lo;
+
     vmx_state->exit_ctrls.host_64_on = 1;
 
     if ((vmx_state->exit_ctrls.save_efer == 1) || (vmx_state->exit_ctrls.ld_efer == 1)) {
         vmx_state->ia32e_avail = 1;
     }
 
-    v3_get_msr(VMX_ENTRY_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
-    vmx_state->entry_ctrls.value = tmp_msr.lo;
 
-    {
-       struct vmx_exception_bitmap excp_bmap;
-       excp_bmap.value = 0;
-       
-       excp_bmap.pf = 1;
-    
-       vmx_ret |= check_vmcs_write(VMCS_EXCP_BITMAP, excp_bmap.value);
-    }
     /******* Setup VMXAssist guest state ***********/
 
     info->rip = 0xd0000;
     info->vm_regs.rsp = 0x80000;
-
-    struct rflags * flags = (struct rflags *)&(info->ctrl_regs.rflags);
-    flags->rsvd1 = 1;
-
-    /* Print Control MSRs */
-    v3_get_msr(VMX_CR0_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
-    PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
-
-    v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
-    PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
-
+    info->ctrl_regs.rflags->rsvd1 = 1;
 
 #define GUEST_CR0 0x80000031
 #define GUEST_CR4 0x00002000
@@ -267,6 +249,9 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
         /* Add CR exits */
         vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
         vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
+       
+       /* Add page fault exits */
+       vmx_state->excp_bmap.pf = 1;
     }
 
     // Setup segment registers
@@ -357,15 +342,28 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
        }
 
        memcpy((void *)vmxassist_dst, v3_vmxassist_start, v3_vmxassist_end - v3_vmxassist_start);
+
+
+       vmx_state->assist_state = VMXASSIST_DISABLED;
     }    
 
-    /*** Write all the info to the VMCS ***/
 
+
+
+    /* Sanity check ctrl/reg fields against hw_defaults */
+
+
+
+    /*** Write all the info to the VMCS ***/
+  
+    {
 #define DEBUGCTL_MSR 0x1d9
-    v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
-    vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
+       struct v3_msr tmp_msr;
+       v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
+       vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
+       info->dbg_regs.dr7 = 0x400;
+    }
 
-    info->dbg_regs.dr7 = 0x400;
 
 #ifdef __V3_64BIT__
     vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
@@ -374,6 +372,9 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
     vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
 #endif
 
+
+ 
+
     if (v3_update_vmcs_ctrl_fields(info)) {
         PrintError("Could not write control fields!\n");
         return -1;
@@ -385,7 +386,6 @@ static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state)
     }
 
 
-    vmx_state->assist_state = VMXASSIST_DISABLED;
 
     // reenable global interrupts for vm state initialization now
     // that the vm state is initialized. If another VM kicks us off, 
@@ -400,6 +400,7 @@ int v3_init_vmx_vmcs(struct guest_info * info, v3_vm_class_t vm_class) {
     int vmx_ret = 0;
     
     vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
+    memset(vmx_state, 0, sizeof(struct vmx_data));
 
     PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
 

diff --git a/palacios/src/palacios/vmx_hw_info.c b/palacios/src/palacios/vmx_hw_info.c
index 3220e52..f50404e 100644 (file)
--- a/palacios/src/palacios/vmx_hw_info.c
+++ b/palacios/src/palacios/vmx_hw_info.c
@@ -103,7 +103,7 @@ int v3_init_vmx_hw(struct vmx_hw_info * hw_info) {
     /* Intel Manual 3B. Sect. G.3.3 */
     if ( ((hw_info->proc_ctrls.req_mask & 0x80000000) == 0) || 
         ((hw_info->proc_ctrls.req_val & 0x80000000) == 1) ) {
-       get_ctrl_caps(&(hw_info->proc_ctrls_2), VMX_PROCBASED_CTLS2_MSR);
+       get_ctrl_caps(&(hw_info->sec_proc_ctrls), VMX_PROCBASED_CTLS2_MSR);
     }
     
     get_cr_fields(&(hw_info->cr0), VMX_CR0_FIXED1_MSR, VMX_CR0_FIXED0_MSR);