icr->dst,
icr->val);
-
switch (icr->dst_shorthand) {
case 0: // no shorthand
PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
apic->lapic_id.val, core->cpu_id, apic, priv_data);
- PrintDebug("Write to address space (%p) (val=%x)\n",
- (void *)guest_addr, *(uint32_t *)src);
+ PrintDebug("apic %u: core %u: write to address space (%p) (val=%x)\n",
+ apic->lapic_id.val, core->cpu_id, (void *)guest_addr, *(uint32_t *)src);
if (msr->apic_enable == 0) {
PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
+ v3_update_timers(info);
+ v3_adjust_time(info);
+
// Conditionally yield the CPU if the timeslice has expired
v3_yield_cond(info);
}
#endif
- v3_update_timers(info);
-
- /* If this guest is frequency-lagged behind host time, wait
- * for the appropriate host time before resuming the guest. */
- v3_adjust_time(info);
-
guest_ctrl->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
//V3_Print("Calling v3_svm_launch\n");
v3_cpu_arch_t cpu_type = v3_get_cpu_type(V3_Get_CPU());
int cpu_valid = 0;
+ V3_Print("************** Guest State ************\n");
v3_print_guest_state(core);
// init SVM/VMX
V3_Print("%p", (void *)(start + i));
for (j = i; (j < (i + 16)) && (j < n); j += 2) {
V3_Print(" ");
- V3_Print("%x", *(uint8_t *)(start + j));
+ V3_Print("%02x", *(uint8_t *)(start + j));
if ((j + 1) < n) {
- V3_Print("%x", *((uint8_t *)(start + j + 1)));
+ V3_Print("%02x", *((uint8_t *)(start + j + 1)));
}
}
V3_Print(" ");