#include <palacios/vmx.h>
#include <palacios/vmm.h>
+#include <palacios/vmx_handler.h>
#include <palacios/vmcs.h>
#include <palacios/vmx_lowlevel.h>
#include <palacios/vmm_lowlevel.h>
#include <palacios/vmm_ctrl_regs.h>
#include <palacios/vmm_config.h>
+#include <palacios/vmm_time.h>
#include <palacios/vm_guest_mem.h>
#include <palacios/vmm_direct_paging.h>
#include <palacios/vmx_io.h>
#include <palacios/vmx_msr.h>
-static addr_t host_vmcs_ptrs[CONFIG_MAX_CPUS] = {0};
+
+#ifndef CONFIG_DEBUG_VMX
+#undef PrintDebug
+#define PrintDebug(fmt, args...)
+#endif
-extern int v3_vmx_exit_handler();
-extern int v3_vmx_vmlaunch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
+static addr_t host_vmcs_ptrs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
+static addr_t active_vmcs_ptrs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
+
+extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
+extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
int ret = 0;
return 0;
}
-#if 0
-// For the 32 bit reserved bit fields
-// MB1s are in the low 32 bits, MBZs are in the high 32 bits of the MSR
-static uint32_t sanitize_bits1(uint32_t msr_num, uint32_t val) {
- v3_msr_t mask_msr;
-
- PrintDebug("sanitize_bits1 (MSR:%x)\n", msr_num);
-
- v3_get_msr(msr_num, &mask_msr.hi, &mask_msr.lo);
-
- PrintDebug("MSR %x = %x : %x \n", msr_num, mask_msr.hi, mask_msr.lo);
-
- val |= mask_msr.lo;
- val |= mask_msr.hi;
-
- return val;
-}
-
-
-
-static addr_t sanitize_bits2(uint32_t msr_num0, uint32_t msr_num1, addr_t val) {
- v3_msr_t msr0, msr1;
- addr_t msr0_val, msr1_val;
-
- PrintDebug("sanitize_bits2 (MSR0=%x, MSR1=%x)\n", msr_num0, msr_num1);
-
- v3_get_msr(msr_num0, &msr0.hi, &msr0.lo);
- v3_get_msr(msr_num1, &msr1.hi, &msr1.lo);
-
- // This generates a mask that is the natural bit width of the CPU
- msr0_val = msr0.value;
- msr1_val = msr1.value;
+static int inline check_vmcs_read(vmcs_field_t field, void * val) {
+ int ret = 0;
- PrintDebug("MSR %x = %p, %x = %p \n", msr_num0, (void*)msr0_val, msr_num1, (void*)msr1_val);
+ ret = vmcs_read(field, val);
- val |= msr0_val;
- val |= msr1_val;
+ if (ret != VMX_SUCCESS) {
+ PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
+ }
- return val;
+ return ret;
}
-#endif
-
static addr_t allocate_vmcs() {
reg_ex_t msr;
}
-static int init_vmx_guest(struct guest_info * info, struct v3_vm_config * config_ptr) {
- struct vmx_data * vmx_info = NULL;
- int vmx_ret = 0;
-
- v3_pre_config_guest(info, config_ptr);
-
- vmx_info = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
-
- PrintDebug("vmx_data pointer: %p\n", (void *)vmx_info);
-
- PrintDebug("Allocating VMCS\n");
- vmx_info->vmcs_ptr_phys = allocate_vmcs();
- PrintDebug("VMCS pointer: %p\n", (void *)(vmx_info->vmcs_ptr_phys));
-
- info->vmm_data = vmx_info;
-
- PrintDebug("Initializing VMCS (addr=%p)\n", info->vmm_data);
-
- // TODO: Fix vmcs fields so they're 32-bit
- PrintDebug("Clearing VMCS: %p\n", (void *)vmx_info->vmcs_ptr_phys);
- vmx_ret = vmcs_clear(vmx_info->vmcs_ptr_phys);
+static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state) {
+ int vmx_ret = 0;
+ struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
- if (vmx_ret != VMX_SUCCESS) {
- PrintError("VMCLEAR failed\n");
- return -1;
- }
+ // disable global interrupts for vm state initialization
+ v3_disable_ints();
PrintDebug("Loading VMCS\n");
- vmx_ret = vmcs_load(vmx_info->vmcs_ptr_phys);
+ vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
+ active_vmcs_ptrs[V3_Get_CPU()] = vmx_info->vmcs_ptr_phys;
+ vmx_state->state = VMX_UNLAUNCHED;
if (vmx_ret != VMX_SUCCESS) {
PrintError("VMPTRLD failed\n");
: "memory"
);
gdtr_base = tmp_seg.base;
- vmx_info->host_state.gdtr.base = gdtr_base;
+ vmx_state->host_state.gdtr.base = gdtr_base;
__asm__ __volatile__(
"sidt (%0);"
: "q"(&tmp_seg)
: "memory"
);
- vmx_info->host_state.idtr.base = tmp_seg.base;
+ vmx_state->host_state.idtr.base = tmp_seg.base;
__asm__ __volatile__(
"str (%0);"
: "q"(&tmp_seg)
: "memory"
);
- vmx_info->host_state.tr.selector = tmp_seg.selector;
+ vmx_state->host_state.tr.selector = tmp_seg.selector;
/* The GDTR *index* is bits 3-15 of the selector. */
struct tss_descriptor * desc = NULL;
#endif
);
- vmx_info->host_state.tr.base = tmp_seg.base;
+ vmx_state->host_state.tr.base = tmp_seg.base;
/********** Setup and VMX Control Fields from MSR ***********/
/* Setup IO map */
- v3_init_vmx_io_map(info);
- v3_init_vmx_msr_map(info);
+
struct v3_msr tmp_msr;
v3_get_msr(VMX_PINBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
/* Add external interrupts, NMI exiting, and virtual NMI */
- vmx_info->pin_ctrls.value = tmp_msr.lo;
- vmx_info->pin_ctrls.nmi_exit = 1;
- vmx_info->pin_ctrls.ext_int_exit = 1;
+ vmx_state->pin_ctrls.value = tmp_msr.lo;
+ vmx_state->pin_ctrls.nmi_exit = 1;
+ vmx_state->pin_ctrls.ext_int_exit = 1;
v3_get_msr(VMX_PROCBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
- vmx_info->pri_proc_ctrls.value = tmp_msr.lo;
- vmx_info->pri_proc_ctrls.use_io_bitmap = 1;
- vmx_info->pri_proc_ctrls.hlt_exit = 1;
- vmx_info->pri_proc_ctrls.invlpg_exit = 1;
- vmx_info->pri_proc_ctrls.use_msr_bitmap = 1;
- vmx_info->pri_proc_ctrls.pause_exit = 1;
+ vmx_state->pri_proc_ctrls.value = tmp_msr.lo;
+ vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
+ vmx_state->pri_proc_ctrls.hlt_exit = 1;
+ vmx_state->pri_proc_ctrls.invlpg_exit = 1;
+ vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
+ vmx_state->pri_proc_ctrls.pause_exit = 1;
+ vmx_state->pri_proc_ctrls.tsc_offset = 1;
+#ifdef CONFIG_TIME_VIRTUALIZE_TSC
+ vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
+#endif
- vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->io_map.arch_data));
+ vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->vm_info->io_map.arch_data));
vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
- (addr_t)V3_PAddr(info->io_map.arch_data) + PAGE_SIZE_4KB);
+ (addr_t)V3_PAddr(info->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
+
- vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->msr_map.arch_data));
+ vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->vm_info->msr_map.arch_data));
v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
- vmx_info->exit_ctrls.value = tmp_msr.lo;
- vmx_info->exit_ctrls.host_64_on = 1;
+ vmx_state->exit_ctrls.value = tmp_msr.lo;
+ vmx_state->exit_ctrls.host_64_on = 1;
- if ((vmx_info->exit_ctrls.save_efer == 1) || (vmx_info->exit_ctrls.ld_efer == 1)) {
- vmx_info->ia32e_avail = 1;
+ if ((vmx_state->exit_ctrls.save_efer == 1) || (vmx_state->exit_ctrls.ld_efer == 1)) {
+ vmx_state->ia32e_avail = 1;
}
v3_get_msr(VMX_ENTRY_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
- vmx_info->entry_ctrls.value = tmp_msr.lo;
+ vmx_state->entry_ctrls.value = tmp_msr.lo;
{
struct vmx_exception_bitmap excp_bmap;
info->ctrl_regs.cr3 = info->direct_map_pt;
- // vmx_info->pinbased_ctrls |= NMI_EXIT;
+ // vmx_state->pinbased_ctrls |= NMI_EXIT;
/* Add CR exits */
- vmx_info->pri_proc_ctrls.cr3_ld_exit = 1;
- vmx_info->pri_proc_ctrls.cr3_str_exit = 1;
+ vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
+ vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
}
// Setup segment registers
#define VMXASSIST_GDT 0x10000
addr_t vmxassist_gdt = 0;
- if (guest_pa_to_host_va(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
+ if (v3_gpa_to_hva(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
PrintError("Could not find VMXASSIST GDT destination\n");
return -1;
}
extern uint8_t v3_vmxassist_end[];
addr_t vmxassist_dst = 0;
- if (guest_pa_to_host_va(info, VMXASSIST_START, &vmxassist_dst) == -1) {
+ if (v3_gpa_to_hva(info, VMXASSIST_START, &vmxassist_dst) == -1) {
PrintError("Could not find VMXASSIST destination\n");
return -1;
}
info->dbg_regs.dr7 = 0x400;
+#ifdef __V3_64BIT__
vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
-
+#else
+ vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL);
+ vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
+#endif
+
if (v3_update_vmcs_ctrl_fields(info)) {
PrintError("Could not write control fields!\n");
return -1;
}
- if (v3_update_vmcs_guest_state(info) != VMX_SUCCESS) {
- PrintError("Writing guest state failed!\n");
- return -1;
+ vmx_state->assist_state = VMXASSIST_DISABLED;
+
+ // reenable global interrupts for vm state initialization now
+ // that the vm state is initialized. If another VM kicks us off,
+ // it'll update our vmx state so that we know to reload ourself
+ v3_disable_ints();
+
+ return 0;
+}
+
+int v3_init_vmx_vmcs(struct guest_info * info, v3_vm_class_t vm_class) {
+ struct vmx_data * vmx_state = NULL;
+ int vmx_ret = 0;
+
+ vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
+
+ PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
+
+ PrintDebug("Allocating VMCS\n");
+ vmx_state->vmcs_ptr_phys = allocate_vmcs();
+
+ PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
+
+ info->vmm_data = vmx_state;
+ vmx_state->state = VMX_UNLAUNCHED;
+
+ PrintDebug("Initializing VMCS (addr=%p)\n", info->vmm_data);
+
+ // TODO: Fix vmcs fields so they're 32-bit
+
+ PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
+ vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
+
+ if (vmx_ret != VMX_SUCCESS) {
+ PrintError("VMCLEAR failed\n");
+ return -1;
}
- v3_print_vmcs();
+ if (vm_class == V3_PC_VM) {
+ PrintDebug("Initializing VMCS\n");
+ init_vmcs_bios(info, vmx_state);
+ } else {
+ PrintError("Invalid VM Class\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+
+int v3_deinit_vmx_vmcs(struct guest_info * core) {
+ struct vmx_data * vmx_state = core->vmm_data;
+
+ V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1);
+
+ V3_Free(vmx_state);
+
+ return 0;
+}
+
+
+static int update_irq_exit_state(struct guest_info * info) {
+ struct vmx_exit_idt_vec_info idt_vec_info;
+
+ check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
+
+ if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("Calling v3_injecting_intr\n");
+#endif
+ info->intr_core_state.irq_started = 0;
+ v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
+ }
+
+ return 0;
+}
+
+static int update_irq_entry_state(struct guest_info * info) {
+ struct vmx_exit_idt_vec_info idt_vec_info;
+ struct vmcs_interrupt_state intr_core_state;
+ struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
+
+ check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
+ check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
- vmx_info->state = VMXASSIST_DISABLED;
+ /* Check for pending exceptions to inject */
+ if (v3_excp_pending(info)) {
+ struct vmx_entry_int_info int_info;
+ int_info.value = 0;
+
+ // In VMX, almost every exception is hardware
+ // Software exceptions are pretty much only for breakpoint or overflow
+ int_info.type = 3;
+ int_info.vector = v3_get_excp_number(info);
+
+ if (info->excp_state.excp_error_code_valid) {
+ check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
+ int_info.error_code = 1;
+
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("Injecting exception %d with error code %x\n",
+ int_info.vector, info->excp_state.excp_error_code);
+#endif
+ }
+
+ int_info.valid = 1;
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
+#endif
+ check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
+
+ v3_injecting_excp(info, int_info.vector);
+
+ } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
+ (intr_core_state.val == 0)) {
+
+ if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
+
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("IRQ pending from previous injection\n");
+#endif
+
+ // Copy the IDT vectoring info over to reinject the old interrupt
+ if (idt_vec_info.error_code == 1) {
+ uint32_t err_code = 0;
+
+ check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
+ check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
+ }
+
+ idt_vec_info.undef = 0;
+ check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
+
+ } else {
+ struct vmx_entry_int_info ent_int;
+ ent_int.value = 0;
+
+ switch (v3_intr_pending(info)) {
+ case V3_EXTERNAL_IRQ: {
+ info->intr_core_state.irq_vector = v3_get_intr(info);
+ ent_int.vector = info->intr_core_state.irq_vector;
+ ent_int.type = 0;
+ ent_int.error_code = 0;
+ ent_int.valid = 1;
+
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("Injecting Interrupt %d at exit %u(EIP=%p)\n",
+ info->intr_core_state.irq_vector,
+ (uint32_t)info->num_exits,
+ (void *)(addr_t)info->rip);
+#endif
+
+ check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
+ info->intr_core_state.irq_started = 1;
+
+ break;
+ }
+ case V3_NMI:
+ PrintDebug("Injecting NMI\n");
+
+ ent_int.type = 2;
+ ent_int.vector = 2;
+ ent_int.valid = 1;
+ check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
+
+ break;
+ case V3_SOFTWARE_INTR:
+ PrintDebug("Injecting software interrupt\n");
+ ent_int.type = 4;
+
+ ent_int.valid = 1;
+ check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
+
+ break;
+ case V3_VIRTUAL_IRQ:
+ // Not sure what to do here, Intel doesn't have virtual IRQs
+ // May be the same as external interrupts/IRQs
+
+ break;
+ case V3_INVALID_INTR:
+ default:
+ break;
+ }
+ }
+ } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
+ // Enable INTR window exiting so we know when IF=1
+ uint32_t instr_len;
+
+ check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
+
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("Enabling Interrupt-Window exiting: %d\n", instr_len);
+#endif
+
+ vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
+ check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
+ }
- v3_post_config_guest(info, config_ptr);
return 0;
}
-static int start_vmx_guest(struct guest_info* info) {
- uint32_t error = 0;
+
+static struct vmx_exit_info exit_log[10];
+
+static void print_exit_log(struct guest_info * info) {
+ int cnt = info->num_exits % 10;
+ int i = 0;
+
+
+ V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
+
+ for (i = 0; i < 10; i++) {
+ struct vmx_exit_info * tmp = &exit_log[cnt];
+
+ V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
+ V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
+ V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
+ V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
+ V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
+
+ cnt--;
+
+ if (cnt == -1) {
+ cnt = 9;
+ }
+
+ }
+
+}
+
+/*
+ * CAUTION and DANGER!!!
+ *
+ * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
+ * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
+ * on its contents will cause things to break. The contents at the time of the exit WILL
+ * change before the exit handler is executed.
+ */
+int v3_vmx_enter(struct guest_info * info) {
int ret = 0;
+ uint32_t tsc_offset_low, tsc_offset_high;
+ struct vmx_exit_info exit_info;
+ struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
+
+ // Conditionally yield the CPU if the timeslice has expired
+ v3_yield_cond(info);
- PrintDebug("Attempting VMLAUNCH\n");
+ // Perform any additional yielding needed for time adjustment
+ v3_adjust_time(info);
- info->run_state = VM_RUNNING;
+ // Update timer devices prior to entering VM.
+ v3_update_timers(info);
- rdtscll(info->time_state.cached_host_tsc);
+ // disable global interrupts for vm state transition
+ v3_disable_ints();
- ret = v3_vmx_vmlaunch(&(info->vm_regs), info, &(info->ctrl_regs));
+
+ if (active_vmcs_ptrs[V3_Get_CPU()] != vmx_info->vmcs_ptr_phys) {
+ vmcs_load(vmx_info->vmcs_ptr_phys);
+ active_vmcs_ptrs[V3_Get_CPU()] = vmx_info->vmcs_ptr_phys;
+ }
+
+
+ v3_vmx_restore_vmcs(info);
+
+
+#ifdef CONFIG_SYMCALL
+ if (info->sym_core_state.symcall_state.sym_call_active == 0) {
+ update_irq_entry_state(info);
+ }
+#else
+ update_irq_entry_state(info);
+#endif
+
+ {
+ addr_t guest_cr3;
+ vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
+ vmcs_write(VMCS_GUEST_CR3, guest_cr3);
+ }
+
+ // Perform last-minute time bookkeeping prior to entering the VM
+ v3_time_enter_vm(info);
+
+ tsc_offset_high = (uint32_t)((v3_tsc_host_offset(&info->time_state) >> 32) & 0xffffffff);
+ tsc_offset_low = (uint32_t)(v3_tsc_host_offset(&info->time_state) & 0xffffffff);
+ check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
+ check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
+
+
+ if (vmx_info->state == VMX_UNLAUNCHED) {
+ vmx_info->state = VMX_LAUNCHED;
+ info->vm_info->run_state = VM_RUNNING;
+ ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
+ } else {
+ V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED);
+ ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
+ }
+
+ // PrintDebug("VMX Exit: ret=%d\n", ret);
if (ret != VMX_SUCCESS) {
+ uint32_t error = 0;
+
vmcs_read(VMCS_INSTR_ERR, &error);
- PrintError("VMLAUNCH failed: %d\n", error);
+ PrintError("VMENTRY Error: %d\n", error);
+
+ return -1;
+ }
+
+ // Immediate exit from VM time bookkeeping
+ v3_time_exit_vm(info);
+
+ info->num_exits++;
+
+ /* Update guest state */
+ v3_vmx_save_vmcs(info);
+
+ // info->cpl = info->segments.cs.selector & 0x3;
+
+ info->mem_mode = v3_get_vm_mem_mode(info);
+ info->cpu_mode = v3_get_vm_cpu_mode(info);
+
+
+ check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
+ check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
+ check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
+ check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
+ check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
+ check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
+ check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
- v3_print_vmcs();
+ //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
+
+ exit_log[info->num_exits % 10] = exit_info;
+
+
+#ifdef CONFIG_SYMCALL
+ if (info->sym_core_state.symcall_state.sym_call_active == 0) {
+ update_irq_exit_state(info);
}
+#else
+ update_irq_exit_state(info);
+#endif
- PrintDebug("Returned from VMLAUNCH ret=%d\n", ret);
+ if (exit_info.exit_reason == VMEXIT_INTR_WINDOW) {
+ // This is a special case whose only job is to inject an interrupt
+ vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value));
+ vmx_info->pri_proc_ctrls.int_wndw_exit = 0;
+ vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
+
+#ifdef CONFIG_DEBUG_INTERRUPTS
+ PrintDebug("Interrupts available again! (RIP=%llx)\n", info->rip);
+#endif
+ }
- return -1;
+ // reenable global interrupts after vm exit
+ v3_enable_ints();
+
+ // Conditionally yield the CPU if the timeslice has expired
+ v3_yield_cond(info);
+
+ if (v3_handle_vmx_exit(info, &exit_info) == -1) {
+ PrintError("Error in VMX exit handler\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+
+int v3_start_vmx_guest(struct guest_info * info) {
+
+ PrintDebug("Starting VMX core %u\n", info->cpu_id);
+
+ if (info->cpu_id == 0) {
+ info->core_run_state = CORE_RUNNING;
+ info->vm_info->run_state = VM_RUNNING;
+ } else {
+
+ PrintDebug("VMX core %u: Waiting for core initialization\n", info->cpu_id);
+
+ while (info->core_run_state == CORE_STOPPED) {
+ v3_yield(info);
+ //PrintDebug("VMX core %u: still waiting for INIT\n",info->cpu_id);
+ }
+
+ PrintDebug("VMX core %u initialized\n", info->cpu_id);
+ }
+
+
+ PrintDebug("VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
+ info->cpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base),
+ info->segments.cs.limit, (void *)(info->rip));
+
+
+ PrintDebug("VMX core %u: Launching VMX VM\n", info->cpu_id);
+
+ v3_start_time(info);
+
+ while (1) {
+
+ if (info->vm_info->run_state == VM_STOPPED) {
+ info->core_run_state = CORE_STOPPED;
+ break;
+ }
+
+ if (v3_vmx_enter(info) == -1) {
+ v3_print_vmcs();
+ print_exit_log(info);
+ return -1;
+ }
+
+
+
+ if (info->vm_info->run_state == VM_STOPPED) {
+ info->core_run_state = CORE_STOPPED;
+ break;
+ }
+/*
+ if ((info->num_exits % 5000) == 0) {
+ V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
+ }
+*/
+
+ }
+
+ return 0;
}
}
static int has_vmx_nested_paging() {
+ /* We assume that both EPT and unrestricted guest mode (Intel's Virtual Real Mode)
+ * are mutually assured. i.e. We have either both or neither.
+ */
+
+
+
return 0;
}
struct v3_msr tmp_msr;
uint64_t ret = 0;
- v3_get_msr(VMX_CR4_FIXED0_MSR,&(tmp_msr.hi),&(tmp_msr.lo));
-
+ v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
+
+#ifdef __V3_64BIT__
__asm__ __volatile__ (
"movq %%cr4, %%rbx;"
"orq $0x00002000, %%rbx;"
:
: "%rbx"
);
+#elif __V3_32BIT__
+ __asm__ __volatile__ (
+ "movl %%cr4, %%ecx;"
+ "orl $0x00002000, %%ecx;"
+ "movl %%ecx, %0;"
+ : "=m"(ret)
+ :
+ : "%ecx"
+ );
+
+ if ((~ret & tmp_msr.value) == 0) {
+ __asm__ __volatile__ (
+ "movl %0, %%cr4;"
+ :
+ : "q"(ret)
+ );
+ } else {
+ PrintError("Invalid CR4 Settings!\n");
+ return;
+ }
+
+ __asm__ __volatile__ (
+ "movl %%cr0, %%ecx; "
+ "orl $0x00000020,%%ecx; "
+ "movl %%ecx, %%cr0;"
+ :
+ :
+ : "%ecx"
+ );
+
+#endif
+
//
// Should check and return Error here....
PrintError("VMX initialization failure\n");
return;
}
-
+
if (has_vmx_nested_paging() == 1) {
v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
}
-void v3_init_vmx_hooks(struct v3_ctrl_ops * vm_ops) {
-
- // Setup the VMX specific vmm operations
- vm_ops->init_guest = &init_vmx_guest;
- vm_ops->start_guest = &start_vmx_guest;
- vm_ops->has_nested_paging = &has_vmx_nested_paging;
-
+void v3_deinit_vmx_cpu(int cpu_id) {
+ extern v3_cpu_arch_t v3_cpu_types[];
+ v3_cpu_types[cpu_id] = V3_INVALID_CPU;
+ V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1);
}
-
