#include <palacios/vmx_io.h>
#include <palacios/vmx_msr.h>
+
+#ifndef CONFIG_DEBUG_VMX
+#undef PrintDebug
+#define PrintDebug(fmt, args...)
+#endif
+
+
static addr_t host_vmcs_ptrs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
/********** Setup and VMX Control Fields from MSR ***********/
/* Setup IO map */
- v3_init_vmx_io_map(info);
- v3_init_vmx_msr_map(info);
+
struct v3_msr tmp_msr;
vmx_state->pri_proc_ctrls.invlpg_exit = 1;
vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
vmx_state->pri_proc_ctrls.pause_exit = 1;
+#ifdef CONFIG_TIME_TSC_OFFSET
+ vmx_state->pri_proc_ctrls.tsc_offset = 1;
+#endif
- vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->io_map.arch_data));
+ vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->vm_info->io_map.arch_data));
vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
- (addr_t)V3_PAddr(info->io_map.arch_data) + PAGE_SIZE_4KB);
+ (addr_t)V3_PAddr(info->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
+
- vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->msr_map.arch_data));
+ vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->vm_info->msr_map.arch_data));
v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
vmx_state->exit_ctrls.value = tmp_msr.lo;
#define VMXASSIST_GDT 0x10000
addr_t vmxassist_gdt = 0;
- if (guest_pa_to_host_va(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
+ if (v3_gpa_to_hva(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
PrintError("Could not find VMXASSIST GDT destination\n");
return -1;
}
extern uint8_t v3_vmxassist_end[];
addr_t vmxassist_dst = 0;
- if (guest_pa_to_host_va(info, VMXASSIST_START, &vmxassist_dst) == -1) {
+ if (v3_gpa_to_hva(info, VMXASSIST_START, &vmxassist_dst) == -1) {
PrintError("Could not find VMXASSIST destination\n");
return -1;
}
check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
- if ((info->intr_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
+ if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
#ifdef CONFIG_DEBUG_INTERRUPTS
PrintDebug("Calling v3_injecting_intr\n");
#endif
- info->intr_state.irq_started = 0;
- v3_injecting_intr(info, info->intr_state.irq_vector, V3_EXTERNAL_IRQ);
+ info->intr_core_state.irq_started = 0;
+ v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
}
return 0;
static int update_irq_entry_state(struct guest_info * info) {
struct vmx_exit_idt_vec_info idt_vec_info;
- struct vmcs_interrupt_state intr_state;
+ struct vmcs_interrupt_state intr_core_state;
struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
- check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_state));
+ check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
/* Check for pending exceptions to inject */
if (v3_excp_pending(info)) {
int_info.valid = 1;
#ifdef CONFIG_DEBUG_INTERRUPTS
- PrintDebug("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)info->rip);
+ PrintDebug("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
#endif
check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
v3_injecting_excp(info, int_info.vector);
} else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
- (intr_state.val == 0)) {
+ (intr_core_state.val == 0)) {
- if ((info->intr_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
+ if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
#ifdef CONFIG_DEBUG_INTERRUPTS
PrintDebug("IRQ pending from previous injection\n");
switch (v3_intr_pending(info)) {
case V3_EXTERNAL_IRQ: {
- info->intr_state.irq_vector = v3_get_intr(info);
- ent_int.vector = info->intr_state.irq_vector;
+ info->intr_core_state.irq_vector = v3_get_intr(info);
+ ent_int.vector = info->intr_core_state.irq_vector;
ent_int.type = 0;
ent_int.error_code = 0;
ent_int.valid = 1;
#ifdef CONFIG_DEBUG_INTERRUPTS
PrintDebug("Injecting Interrupt %d at exit %u(EIP=%p)\n",
- info->intr_state.irq_vector,
+ info->intr_core_state.irq_vector,
(uint32_t)info->num_exits,
- (void *)info->rip);
+ (void *)(addr_t)info->rip);
#endif
check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
- info->intr_state.irq_started = 1;
+ info->intr_core_state.irq_started = 1;
break;
}
*/
int v3_vmx_enter(struct guest_info * info) {
int ret = 0;
- uint64_t tmp_tsc = 0;
+ uint32_t tsc_offset_low, tsc_offset_high;
struct vmx_exit_info exit_info;
// Conditionally yield the CPU if the timeslice has expired
v3_yield_cond(info);
-
// v3_print_guest_state(info);
// disable global interrupts for vm state transition
v3_vmx_restore_vmcs(info);
-#ifdef CONFIG_SYMBIOTIC
- if (info->sym_state.sym_call_active == 0) {
+#ifdef CONFIG_SYMCALL
+ if (info->sym_core_state.symcall_state.sym_call_active == 0) {
update_irq_entry_state(info);
}
#else
vmcs_write(VMCS_GUEST_CR3, guest_cr3);
}
- rdtscll(info->time_state.cached_host_tsc);
+ v3_update_timers(info);
+ v3_resume_time(info);
+
+ tsc_offset_high =
+ (uint32_t)((info->time_state.host_offset >> 32) & 0xffffffff);
+ tsc_offset_low = (uint32_t)(info->time_state.host_offset & 0xffffffff);
+#ifdef CONFIG_TIME_TSC_OFFSET
+ check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
+ check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
+#endif
- if (info->run_state == VM_STOPPED) {
- info->run_state = VM_RUNNING;
+ PrintDebug("Stored 0x %x %x into vmcs TSC offset.\n",
+ tsc_offset_high, tsc_offset_low);
+ if (info->vm_info->run_state == VM_STOPPED) {
+ info->vm_info->run_state = VM_RUNNING;
ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
} else {
ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
return -1;
}
- rdtscll(tmp_tsc);
+ v3_pause_time(info);
+#ifdef CONFIG_TIME_MASK_OVERHEAD
+ v3_offset_time(info, -VMX_ENTRY_OVERHEAD);
+#endif
info->num_exits++;
- v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
-
/* Update guest state */
v3_vmx_save_vmcs(info);
exit_log[info->num_exits % 10] = exit_info;
-#ifdef CONFIG_SYMBIOTIC
- if (info->sym_state.sym_call_active == 0) {
+#ifdef CONFIG_SYMCALL
+ if (info->sym_core_state.symcall_state.sym_call_active == 0) {
update_irq_exit_state(info);
}
#else
PrintDebug("Launching VMX guest\n");
- rdtscll(info->time_state.cached_host_tsc);
-
+ v3_start_time(info);
while (1) {
if (v3_vmx_enter(info) == -1) {
uint64_t ret = 0;
v3_get_msr(VMX_CR4_FIXED0_MSR,&(tmp_msr.hi),&(tmp_msr.lo));
-
+#ifdef __V3_64BIT__
__asm__ __volatile__ (
"movq %%cr4, %%rbx;"
"orq $0x00002000, %%rbx;"
:
: "%rbx"
);
+#elif __V3_32BIT__
+ __asm__ __volatile__ (
+ "movl %%cr4, %%ecx;"
+ "orl $0x00002000, %%ecx;"
+ "movl %%ecx, %0;"
+ : "=m"(ret)
+ :
+ : "%ecx"
+ );
+
+ if ((~ret & tmp_msr.value) == 0) {
+ __asm__ __volatile__ (
+ "movl %0, %%cr4;"
+ :
+ : "q"(ret)
+ );
+ } else {
+ PrintError("Invalid CR4 Settings!\n");
+ return;
+ }
+
+ __asm__ __volatile__ (
+ "movl %%cr0, %%ecx; "
+ "orl $0x00000020,%%ecx; "
+ "movl %%ecx, %%cr0;"
+ :
+ :
+ : "%ecx"
+ );
+
+#endif
+
//
// Should check and return Error here....
