#define MASK(val, length) ({ \
- ullong_t mask = 0x0LL; \
+ uint64_t mask = 0x0LL; \
switch (length) { \
case 1: \
mask = 0x00000000000000ffLL; \
break;
}
+ case MOVSX_8:
+ case MOVZX_8: {
+ uint8_t reg_code = 0;
+
+ ret = decode_rm_operand(core, instr_ptr, form, instr, &(instr->src_operand), ®_code);
+ instr->src_operand.size = 1;
+
+ if (ret == -1) {
+ PrintError("Error decoding operand\n");
+ return -1;
+ }
+
+ instr_ptr += ret;
+
+ instr->dst_operand.size = operand_width;
+ instr->dst_operand.type = REG_OPERAND;
+ decode_gpr(core, reg_code, &(instr->dst_operand));
+
+ instr->src_operand.read = 1;
+ instr->dst_operand.write = 1;
+
+ instr->num_operands = 2;
+
+ break;
+ }
+ case MOVSX:
+ case MOVZX: {
+ uint8_t reg_code = 0;
+
+ ret = decode_rm_operand(core, instr_ptr, form, instr, &(instr->src_operand), ®_code);
+ instr->src_operand.size = 2;
+
+ if (ret == -1) {
+ PrintError("Error decoding operand\n");
+ return -1;
+ }
+
+ instr_ptr += ret;
+
+ instr->dst_operand.size = operand_width;
+ instr->dst_operand.type = REG_OPERAND;
+ decode_gpr(core, reg_code, &(instr->dst_operand));
+
+ instr->src_operand.read = 1;
+ instr->dst_operand.write = 1;
+
+ instr->num_operands = 2;
+
+ break;
+ }
case ADC_IMM2SX_8:
case ADD_IMM2SX_8:
case AND_IMM2SX_8:
instr->src_operand.type = IMM_OPERAND;
instr->src_operand.size = operand_width;
- instr->src_operand.operand = *(sint8_t *)instr_ptr; // sign extend.
+ instr->src_operand.operand = (addr_t)MASK((sint64_t)*(sint8_t *)instr_ptr, operand_width); // sign extend.
instr->src_operand.read = 1;
instr->dst_operand.write = 1;
ret = decode_rm_operand(core, instr_ptr, form, instr, &(instr->dst_operand),
®_code);
-
if (ret == -1) {
PrintError("Error decoding operand for (%s)\n", op_form_to_str(form));
return -1;
}
instr_ptr += ret;
-
+
instr->src_operand.type = REG_OPERAND;
instr->src_operand.size = operand_width;
decode_cr(core, reg_code, &(instr->src_operand));
case STOS:
case STOS_8: {
instr->is_str_op = 1;
-
+
if (instr->prefixes.rep == 1) {
instr->str_op_length = MASK(core->vm_regs.rcx, operand_width);
} else {
instr->str_op_length = 1;
}
-
+
instr->src_operand.size = operand_width;
instr->src_operand.type = REG_OPERAND;
instr->src_operand.operand = (addr_t)&(core->vm_regs.rax);
-
+
instr->dst_operand.type = MEM_OPERAND;
instr->dst_operand.size = operand_width;
instr->dst_operand.operand = get_addr_linear(core, MASK(core->vm_regs.rdi, addr_width), &(core->segments.es));
-
+
instr->src_operand.read = 1;
instr->dst_operand.write = 1;
-
+
instr->num_operands = 2;
-
+
break;
}
case INVLPG: {
case MOV_2CR:
return V3_OP_MOV2CR;
+ // KCH: for syscall interposition
+ case INT:
+ return V3_OP_INT;
+
case MOV_MEM2_8:
case MOV_MEM2: